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AVR microprocessor implementation on FPGA
Hájek, Radek ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This bachelor‘s thesis deals with FPGA implementation of Atmel AVR core described using VHDL language. Basic architecture concepts and processor addressing modes are summarized in this thesis. The core including several peripherals was designed to be compatible with ATtiny26 architecture and instruction set. The microprocessor was described in VHDL and verified in several types of tests.
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Remote control of targets
Tkáč, Stanislav ; Frýza, Tomáš (referee) ; Jakubová, Ivana (advisor)
The task of this work is to make a functional device, that is intended to close only one of several (38 to 55) of electromagnetic valves. Which valve is going to be switched is elected either of the push-button keypad, or from a PC via RS 232. Equipment must be made using one or more PIC processors.
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Universal BLDC motor controller
Pijáček, Ondřej ; Pohl, Lukáš (referee) ; Veselý, Libor (advisor)
This thesis describes the design of universal control unit for BLDC motor powered from airplane power distribution system of 28 V capable of driving motor up to 10 A. The maximal engine power is about 250 W. Important prerequisite is possibility of driving various motor size without needs of changing wiring board using only the configuration in the auxiliary memory unit. To control different motors is enough one unit with one program without any way to interfere to the unit itself.
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Emulator of Simple Processor
Kuzník, Petr ; Přikryl, Zdeněk (referee) ; Křoustek, Jakub (advisor)
Emulator will be designed as generic emulator. It should be capable of emulating versatile architectures. Each architecture will be stored in separate module implemented as dynamically linked dll libraries. Main goal is for the emulator to be generic and design its structure in a way, so that it would be possible to easily add new architecture modules and design these modules with already implemented abstractions. Primarily implemented architecture will be Commodore 64. It is a personal computer used mainly in USA during 1980s.
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Software Multi-Effect for Post-Production of Pop Music
Trkal, Tomáš ; Glembek, Ondřej (referee) ; Černocký, Jan (advisor)
This diploma thesis deals with design and implementation of complex software system for post-production of popular music. The system was implemented as a plug-in module in C++ language using JUCE application framework. The emphasis was on creating a well arranged and intuitive graphic user interface. The plug-in provides a set of audio effects and processors that can be connected into the desired graph structure. For less experienced users, there is a database of preset configurations usable for a variety of input signals.
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Instruction level parallelism in modern processors
Sláma, Pavel ; Levek, Vladimír (referee) ; Pristach, Marián (advisor)
Basic methodology that exploits instruction level parallelism is called pipelining and it is part of every processor for decades. The ideal pipeline increases performance and efficiency for a relatively small cost. But the real pipeline has number of limitations caused by dependencies and hazards between instructions. The aim of this thesis is to discuss techniques used to improve efficency and performance of pipelined processors, to implement selected techniques to a RISC processor model and discuss its benefits.
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Processor Overclocking
Horký, Jan ; Adámek, Martin (referee) ; Novotný, Radovan (advisor)
The aim of bachelor's thesis was to describe and explain processor overclocking and its use. Suitable processor was chosen and its operational frequency was increased by increasing value of multiplier and changing frequency of FSB. Multiplier and frequency of FSB were increased by the smallest step, which motherboard allowed, to value when computer was unstable. Processor was tested by stress and performance tests for each frequency. Change of power consumption was also measured. At the end, both methods were compared.
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Modelling of 8051 Processor
Krůpa, Tomáš ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
Computer modeling is nowadays very important part of development of almost any new product. The objective of this bachelors thesis is to develop a model of 8051 microprocessor that should enlarge a portfolio of customizable processors available for Codasip platform. The complete model is described in two levels of abstraction the instruction accurate model and the cycle accurate model. For verification of the model, ANSI C programs translated by SDCC compiler were used.
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Framework for RISC-V Compliance Tests Execution
Skála, Milan ; Čekan, Ondřej (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.
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