National Repository of Grey Literature 66 records found  1 - 10nextend  jump to record: Search took 0.01 seconds. 
Verification environment for BLDC motor controller
Kalocsányi, Vít ; Kajan, Michal (referee) ; Dvořák, Vojtěch (advisor)
Tato práce se věnuje požadavku na důkladnou verifikaci při návrhu systému řízení BLDC motorů. V práci je vysvětlena funkční verifikace číslicových obvodů a univerzální verifikační metodika (UVM) a práce je zaměřena na návrh verifikačního prostředí s využitím této metodologie. Dále je v této práci vysvětlena typická struktura systému řízení BLDC motoru a definován způsob verifikace takového systému řízení. Dále je popsána implementace verifikačního prostředí a diskutovány přínosy zavedení UVM do verifikačního procesu.
Hardware Accelerated Functional Verification
Zachariášová, Marcela ; Kotásek, Zdeněk (referee) ; Kajan, Michal (advisor)
Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.
AVR32 Model Coreation
Sarčák, Rostislav ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
This barchelor's thesis describe creation of AVR32 processor instruction-accurate model using CodAL language. In this thesis RISC AVR32 architecture, approach to implementation of the model, testing and generating of software toolchain is described. Model development is realized in Codasip framework. Model contains implementation of AVR32 instruction set. The result of this work is AVR32 processor instruction-accurate model.
Management System for Sports Teams
Nowak, Jakub ; Kajan, Michal (referee) ; Korček, Pavol (advisor)
The thesis is focused on problematic of sports team management. It analyzes sports team‘s needs and requirements for a system, which could help them to organize their team activities and issues. Thesis includes an implementation of such system and its marketing strategy for future development purposes. Whole system is built on a web application basis using PHP programming language and relational database server MariaDB. System is available online for public use. It is monitored continuously and its expansion and development is based on feedbacks from its users.
Packet Filtering in Computer Networks
Faron, Jan ; Kováčik, Michal (referee) ; Kajan, Michal (advisor)
This bachelor’s thesis deals with packet classification in computer networks. In the introduction it describes some areas where packet classification is used. Then, necessary theoretical background is introduced, together with requirements for classification algorithm. It describes four high-level approaches to the packet classification. It describes principle of various algorithms for each high-level approach. Algorithm EffiCuts is chosen for detailed analysis and implementation. This packet classification algorithm is compared with other packet classification algorithms from NetBench library.
Random Numbers Generator with Selected Distribution
Kajan, Michal ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis describes random numbers generating techniques. First part focuses on methods of obtaining pseudorandom numbers and presents typical examples of random numbers generators. This part also contains description of distribution transformation methods of random numbers and briefly deals with testing of statistical properties of random numbers generators. Following part describes LFSR generator in detail as one of most widely used generators for hardware applications. In addition, description of transformation process and implementation of circuit calculating transformation to the exponential distribution is included. Last part contains resources requierements of designed circuits for implementation in FPGA.
Lossless Data Compression for IP Networks
Pánek, Richard ; Kajan, Michal (referee) ; Korček, Pavol (advisor)
This bachelor's thesis deals with data compression methods in IP networks. The LZW compression algorithm and its history is described more in detail. This algorithm is tested on the di erent types of IP tracffic. It is shown that depending on the traffic type it is possible to reduce data to 70% of its original size. As the final implementation of the LZW algorithm is intented for use in the FPGA the results from high level synthesis (from C to VHDL language) are fi nally described.
Packet Filtering in Computer Networks
Holuša, Jan ; Kováčik, Michal (referee) ; Kajan, Michal (advisor)
This bachelor's thesis deals with packet classification in computer networks. It describes algorithms which are implemented in experimental Netbench framework. For some of them, there are examples of data structures and searching methods. Part of this thesis is implementation of modular packet classification algorithm. Another part of this thesis describes experiments with this algorithm to find its suitable parameters and experiments with Netbench algorithms for comparison of their space and computational complexity.
Acceleration of Network Traffic Encryption
Koranda, Karel ; Kajan, Michal (referee) ; Polčák, Libor (advisor)
This thesis deals with the design of hardware unit used for acceleration of the process of securing network traffic within Lawful Interception System developed as a part of Sec6Net project. First aim of the thesis is the analysis of available security mechanisms commonly used for securing network traffic. Based on this analysis, SSH protocol is chosen as the most suitable mechanism for the target system. Next, the thesis aims at introduction of possible variations of acceleration unit for SSH protocol. In addition, the thesis presents a detailed design description and implementation of the unit variation based on AES-GCM algorithm, which provides confidentiality, integrity and authentication of transmitted data. The implemented acceleration unit reaches maximum throughput of 2,4 Gbps.
Acceleration of Microscopic Urban Traffic Simulation Using OpenCL
Urminský, Andrej ; Kajan, Michal (referee) ; Korček, Pavol (advisor)
As the number of vehicles on our roads increases, the problems related to this phenomenon emerge more dramatically. These problems include car accidents, congestions and CO2 emissions production, increasing CO2 concentrations in the atmosphere. In order to minimize these impacts and to use the road infrastructure eff ectively, the use of traffic simulators can come in handy. Thanks to these tools, it is possible to evaluate the evolution of a traffic flow with various initial states of the simulation and thus know what to do and how to react in different states of the real-world traffic situations. This thesis deals with acceleration of microscopic urban traffic simulation using OpenCL. Supposing it is necessary to simulate a large network traffic, the need to accelerate the simulation is necessary. For this purpose, it is possible, for example, to use the graphics processing units (GPUs) and the technique of GPGPU for general purpose computations, which is used in this work. The results show that the performance gains of GPUs are significant compared to a parallel implementation on CPU.

National Repository of Grey Literature : 66 records found   1 - 10nextend  jump to record:
See also: similar author names
1 Kajan, Martin
3 Kajan, Matej
4 Kajan, Miroslav
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