National Repository of Grey Literature 101 records found  1 - 10nextend  jump to record: Search took 0.00 seconds. 
Training tracking using NFC technology
Blažík, Vojtěch ; Zachariášová, Marcela (referee) ; Strnadel, Josef (advisor)
This bachelor thesis describes the development of mobile application which uses NFC technology for training tracking and monitoring of gym equipment usage. The work summarizes the basic motivation and approaches to training and equipment tracking as well as NFC technology and mobile app development focused on the multiplatform framework Flutter. The resulting app is based on the client-server architecture with offline mode support and uses the identifiers of deployed NFC tags to identify the machine and exercises. The goal of this work is to show a functional system, which incorporates this technology in an unconventional way to achieve a higher user comfort.
System for Electricity Consumption Registration
Hockicko, Matej ; Zachariášová, Marcela (referee) ; Mrázek, Vojtěch (advisor)
The aim of this work is to design a system to record the consumed electricity. This system will consist of an embedded device that monitors the optical output of the meter and a mobile application, which will be able to download and display the measured data using bluetooth technology. The embedded system will consist of a microcontroller from Nordic Semiconductor. The mobile application will be programmed in the Flutter framework. Historically measured data will be stored on the cloud. The focus of the design will be on the battery life of the embedded device, which will be powered by a CR2032 battery. The main benefit of this work is the ability to monitor electricity consumption using the embedded device and mobile application without the need of owning a smart meter.
Simulace a optimalizace metod DNA výpočtů
Plevač, Lukáš ; Zachariášová, Marcela (referee) ; Bidlo, Michal (advisor)
This work focuses on creating a program for simulating the SIMD||DNA computation architecture and subsequently utilizing this simulation to design new algorithms for this architecture, such as shift registers, 3-state cellular automata, or LFSR registers. SIMD||DNA belongs to the field of DNA computing architectures, which represent an unconventional computing method entirely different from today’s electronic computers. The main principle of DNA computing involves leveraging DNA properties for information processing. This method offers advantages in energy efficiency and massive parallelism, theoretically capable of surpassing current limits in information processing. It also provides higher information storage density, leading to the emergence of a new type of storage known as DNA digital data storage. SIMD||DNA is an architecture aimed at performing computations with data stored in this manner.
Implementation of system for IC testing via JTAG interface
Prášil, Pavel ; Zachariášová, Marcela (referee) ; Petyovský, Petr (advisor)
This master thesis deals with testing integrated circuits containing RISC-V processor core using JTAG protocol. This thesis objective is to design a module for 2-wire JTAG protocol support and design of an extending protocol for RISC-V processor system bus access. Designed module will be used for the integrated circuit testing using a 2-wire JTAG interface in order to reduce the number of pins dedicated for JTAG interface. The extending protocol will be used to reduce time spent by integrated circuits testing. The thesis contains description of the RISC-V testing system, design and implementation of module for 2-wire JTAG protocol support and also design and implementation of module for system bus access by the extending protocol. The thesis also includes extension of testing SW environment by support of communication using the extending protocol and verification of HW solution functionality. The thesis contain evaluation of time efficiency of implemented communication solution.
Hardware Accelerated Functional Verification
Zachariášová, Marcela ; Kotásek, Zdeněk (referee) ; Kajan, Michal (advisor)
Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.
Specialized Instruction Design
Koscielniak, Jan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The purpose of this thesis is to design and implement specialized instructions for RISC-V instruction set architecture. These instruction are used to accelerate a set of selected cryptographic algorithms. New instructions are implemented in Codasip Studio for 32bit processor model with RV32IM instruction set. Open source implementations were selected and edited to use new instructions. Instructions were used on respective algorithms, tested and profiled. The outcome of this thesis is instruction set extension, that enables up to seven times speed up, depending on used algorithm.
Evolutionary Analogue Amplifier Optimisation
Bielik, Marek ; Zachariášová, Marcela (referee) ; Bidlo, Michal (advisor)
Táto práca demonštruje možnosti využitia evolučných algoritmov, konkrétne evolučných stratégií, v doméne dizajnu analógových zosilňovačov. Do implementácie je zahrnutý ngSPICE simulátor, ktorý je použitý na vyhodnotenie optimalizovaných riešení a v práci je navrhnutých niekoľko vyhodnocovacích metód. Práca tiež zahŕňa experimenty a ich výsledky, ktoré boli použité na určenie najvodnejších parametrov evolučných stratégií. Cieľom bolo optimalizovať hodnoty súčiastok jedno a dvoj stupňových zosilňovačov s bipolárnymi tranzistormi v zapojení so spoločným emitorom. Výsledkom je nástroj umožňujúci návrh zosilňovačov s ľubovoľným zosilnením v rámci možností daného obvodu bez použitia akéhokoľvek matematického aparátu.
Coevolutionary Algorithms Statistical Analysis Tool
Urban, Daniel ; Zachariášová, Marcela (referee) ; Drahošová, Michaela (advisor)
This bachelor thesis contains a theoretical basis that introduces evolutionary algorithms, genetic programming, coevolutioanary algorithms and methods for statistical evaluation. Furthermore, this work deals with the design and implementation of tool with graphical user interface, which allows the analysis of coevolutioanary algorithm for various parameters and also its statistical evaluation. The functionality of the implemented tool has been tested on data obtained from an external program performing evolutionary design of image filters with the use of the coevolution of tness predictors. The resulting graphs and statistics allow easy comparison of the progress and results for each program run.
Design and Implementation of a Profiler for ASIPs
Richtarik, Pavel ; Hynek, Jiří (referee) ; Zachariášová, Marcela (advisor)
The major objective of this work is to analyse possibilities of profiling application specific instruction-set processors, to explore some common profiling techniques and to use the collected information to design and implement a new profiling tool suitable for utilization in the processors development and optimization. This bachelor thesis presents requirements on the new profiler and describes its key parts from the design and the implementation perspective.
Portable Stimulus Scenarios Specification for RISC-V Processor Modules
Bardonek, Petr ; Bidlo, Michal (referee) ; Zachariášová, Marcela (advisor)
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.

National Repository of Grey Literature : 101 records found   1 - 10nextend  jump to record:
See also: similar author names
1 ZACHARIÁŠOVÁ, Marie
2 Zachariášová, Miroslava
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