Original title: Paralelismus na úrovni instrukcí v moderních procesorech
Translated title: Instruction level parallelism in modern processors
Authors: Sláma, Pavel ; Levek, Vladimír (referee) ; Pristach, Marián (advisor)
Document type: Master’s theses
Year: 2020
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]

Keywords: CodAL; Codasip Studio; Codasip uRISC; multiple issue; pipeline; Processor; RISC; Tomasulo algorithm; CodAL; Codasip Studio; Codasip uRISC; metoda vydávání více instrukcí za takt; Procesor; RISC; Tomasulův algoritmus; zřetězená linka

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/189372

Permalink: http://www.nusl.cz/ntk/nusl-585539


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2024-04-02, last modified 2024-04-03


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