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FFT implementation in FPGA and ASIC
Dvořák, Vojtěch ; Bohrn, Marek (referee) ; Fujcik, Lukáš (advisor)
The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
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Test Planning Tool Extension for Distributed Systems
Mészáros, Filip ; Ráb, Jaroslav (referee) ; Ščuglík, František (advisor)
This bachelor thesis is about automatical software testing using the testing scheduler. It describes creation of the extension for the existing testing scheduler, so it will be possible to split effectively a group of tests to segments, that will be executed independently on each other. Tests are splitted according to the common characteristics of the enviroment, that need to be prepared for each test, and according to the dependencies between the tests. Furthermore, it describes what optimizations are used for splitting of the tests to subsets. Each subset of the tests runs on a standalone testing system, so the time needed for succesful completion of testing with the given set of tests is reduced. Created tool is succesfully used during everyday testing of the several products in the Acision company, to which was this tool made.
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Functional Verification Framework for Multi Buses Following the UVM Standard
Beneš, Tomáš ; Šišmiš, Lukáš (referee) ; Kekely, Lukáš (advisor)
This thesis focus on the design and subsequent implementation of a multi-bus verification environment using the principles of the Universal Verification Methodology (UVM). It also focus on the implementation of the verification of three FPGA components using multi-bus as input and output interfaces. The implementation of the environment and all verifications is written in SystemVerilog language using a library that implement the basic constructs for UVM. The achieved results of the work are functional and easily reusable when creating further verifications using multi-bus. The proposed environments can be used as a structure for creating other verification environments for other buses.
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Biometry based on retinal videosequences
Oweis, Kamil ; Odstrčilík, Jan (referee) ; Kolář, Radim (advisor)
The biometric methods are the most advanced methods for recognition and verification of person identity. These methods are quite fast, safe and applicable in different situations. In this thesis is used a set of retinal scans taken with a video-ophtalmoscope. These pictures are further modified for next processing, first of all by convertion into black-andwhite binary image, in some cases was after that used a binary matrix for description of image. Afterwards was suggested comparison method of images from the database with reference image of the retina: method of overlap and shift. It was tested a set of blackand-white and then also grey images. All method calculations was realized in program Matlab of which outcome was determination of the most congruent image with reference image and evaluation of overall program accuracy.
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Handwriting and Signature Verification
Beránek, Jan ; Řezníček, Ivo (referee) ; Španěl, Michal (advisor)
This paper concerns methods of verification of person's signature and handwriting. Some of commonly used techniques are resumed and described with related literature being referred. Next aim of this work is design and implementation of a simple handwriting verification application. Application is based on edge detection and comparison of a set of structural and statistical features. As a support classification tool a SVM classifier of the LIBSVM software is employed. The Application is written in C language using OpenCV graphics library. Testing and training set was extracted from samples found in the IAM Handwriting Database. Application was created and tested in the Windows XP operating system.
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Data Structure Visualization for Verification Tools
Holubec, Michael ; Lengál, Ondřej (referee) ; Peringer, Petr (advisor)
The aim of my bachelor thesis is an object-oriented design and implementation of a library which will provide a unified interface to a verification tool Predator and other tools for making a vizualization of data structures primarily for debuging purposes. This work analyses some qualities of the verification tool Predator, Forester and CPAchecker. The library offers not only a graphic but also a text-based output in DOT language. The result has been tested by connecting to the verification tool Predator.
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Test Driven Development for FPGA Designs
Halász, Dávid ; Strnadel, Josef (referee) ; Šimek, Václav (advisor)
Tato bakalářská práce popisuje, jak může být princip TDD uplatněn u hardware, převážně pro vývoj FPGA. Je popsána důležitá teorie pro pochopení kontextu. Na referenčním návrhu jsou představeny některé dostupné a užitečné verifikační nástroje. Jeden z těchto nástrojů byl vybrán a pomocí TDD byl vytvořen a úspěšně otestován návrh komunikačního modulu SPI.
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Models and simulations of processes of emission-free wheel loader with electric drive
Cieslar, Filip ; Nevrlý, Josef (referee) ; Němec, Zdeněk (advisor)
This diploma thesis deals with the creation of models simulating the processes of an emission-free wheel loader, which was created by rebuilding the original version with a combustion engine. Part of the work is the methodical creation of models from the basic part of the machine to a simplified model of the overall machine, its functional verification and calibration based on available information’s and measurements. In this paper, selected parameters of the overall machine model are verified based on performed measurements, the suitability of selected components is verified, and the optimization and modification of the model is performed based on verification. The aim of the thesis is to present the simulation and verification procedure and its practical use in the development of an emission-free wheel loader with electric drive.
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Hydraulic analysis of the supply pipeline to the Kravsko reservoir in Znojmo city
Jaroš, Zdeněk ; Lušovský, Michal (referee) ; Ručka, Jan (advisor)
This thesis provides hydraulic analysis of an existing water supply pipeline from Kasárna reservoir to Kravsko reservoir near Znojmo. The thesis structure is divided into two parts – the first is theoretical, the second part is a practical research. The theoretical part outlines currently used procedures, principles and available software programs. Thesis concentrates on a software called EPANET 2.0 which is also used for hydraulic analysis. In the research part, the thesis offers a description of the chosen site, a field survey followed by the process of assessment and a construction of a hydraulic model by the EPANET 2.0 software. The final part evaluates performed hydraulic analysis and proposes concepts for water supply pipeline renovation.
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AUTOMATED TESTING OF 10GbE DEVICES
Avramović, Nikola ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Tato práce se zabývá návrhem modelu pro funkční verifikaci a návrhem syntetizovatelného testru 10Gb Ethernet zařízení, které používají XGMII rozhraní. Pro popis modelu je použit programovací jazyk VHDL. Práce zahrnuje vytváření bus functional modelu a návrh testru, který se implementuje jako genericky self-test modul. Výsledný návrh umožňuje verifikaci a testování PHY a MAC vrstve. Pro implementaci testru byla použita vývojová deska DE5-Net osazena FPGA obvodem Stratix V GX od firmy Altera.
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