National Repository of Grey Literature 132 records found  1 - 10nextend  jump to record: Search took 0.01 seconds. 
Physiocrate: A SignalPlant Toolbox for Respiratory, Blood Pressure and EMG Signal Analysis
Nejedlý, Petr ; Virgala, Jan
The paper presented here describes the SignalPlant library for analysis of physiological signals. This library contains plugins for analysis of continuous blood pressure (BP), respiratory signals (RESP) and electromyographic signals (EMG). Its principal advantages are real-time previews of results, ease of use and a multi-thread approach. The library is available free and open- source under an MIT license as part of the SignalPlant project at https://signalplant.codeplex.com.
Simple Window Manager for X Window System
Zajdák, Jiří ; Smrčka, Aleš (referee) ; Peringer, Petr (advisor)
Goal of the project is the creation of the simple window manager for X Window System. At first there are explained the principles of work of the graphic applications then the design of window manager and its implementation in the text. The window manager decorates the top-level windows of applications frames which contain functional buttons. For an easily operating are supported virtual screens and hot keys. The panel intended for graphic of plugins, which are implemented as shared libraries, is set in the bottom part of the screen The application place emphasis on minimal memory requirement.
Procedural Generation in Unity
Goš, Pavel ; Chlubna, Tomáš (referee) ; Milet, Tomáš (advisor)
The goal of this thesis is to develop a procedural generator of dungeons in the Unity game engine. The description of the most important parts of the Unity engine can be found in this thesis. The development and implementation of procedural generation of map layout using Perlin noise and interior decoration is described here as well.
Advanced Source Code Editor for a Given Language
Srna, Pavol ; Burgetová, Ivana (referee) ; Eysselt, Miloš (advisor)
Aim of this BSc Thesis is to acquaint with application programming interface of eclipse development environment and to extend appropriately its source code editor to obtain the characteristics of the advanced text editors in the language SIT. The Thesis describes the creation of the parser and lexer from ANTLR grammar. It explains the way of writing plugins to the eclipse platform by focusing on the source code editor. The implemented editor plugin has the support of syntax highlighting, a syntax checking, an automatic code completion and a context information.
Native Code Web Browser Extensions
Vítek, Vojtěch ; Očenášek, Pavel (referee) ; Burget, Radek (advisor)
Nowadays, web applications and browsers are undergoing rapid development - we can say that the progress of Internet technologies is unstoppable phenomenon of the last decade. The need for the best-possible CPU performance in web applications to achieve a smooth user experience is enormous - besides the continuous improvements of existing technologies, we can see several new technologies arising every year. This thesis deals with development of native code web browser extensions whose primary purpose is to use maximum CPU performance as well as efforts to improve the user experience when viewing web pages.
Path Planning using Voronoi Graphs
Živčák, Adam ; Uhlíř, Václav (referee) ; Rozman, Jaroslav (advisor)
The main purpose of this bachelor thesis is to design and implement plugin for robot operating system, which will be used for path planning using Voronoi graphs. Path planning is executed in well known world, about which robot knows where obstacles are placed. Thesis contains overview of main concepts of robot operating system, description of Voronoi graphs and algorithms to construct them. In conclusion is placed comparison of implemented plugin for path planning with ROS integrated planners.
Protecting Local Network Using NetFlow
Hanousek, Vít ; Polčák, Libor (referee) ; Matoušek, Petr (advisor)
This bachelor's thesis deals with the use of NetFlow data for monitoring local networks. There is an analysis of the best known threads for a local network in the first part of the thesis. Detection algorithms based on signature NetFlow detection were implemented for the chosen threads. Four plugins for an open-source application NfSen are outputs of this thesis. These plugins detects the following threads: vertical and horizontal scans, dictionary based attacks on SSH protocol, spam machines.
Time Scheduling Plugin for Kanboard.org
Holubář, Jiří ; Květoňová, Šárka (referee) ; Ščuglík, František (advisor)
Nowadays, in most corporations must be tasks split between more than one person. Simultaneously one person work on more tasks at the same time. That is the reason, why people must plan their work, to achieve maximum efficiency. To do that, the module for Kanboard, which I describe in this work, should be used.
Traffic generator of industrial protocols
Šnajdr, Václav ; Blažek, Petr (referee) ; Martinásek, Zdeněk (advisor)
This bachelor thesis deals with generating data traffic of industrial SCADA protocols and their implementation into JMeter tool. This tool can be expanded with plugins. Three protocols DNP3, IEC61850 and IEC60870-5 are described in the theoretical part. The practical part is devoted to the design and implementation of the DNP3 protocol module and partly to the design of the IEC61850 protocol. The DNP3 module has been functionally tested. There is also an attempt to obtain the TASE.2 library.
Hardware Modelling in UGE
Varga, Ladislav ; Očenášek, Pavel (referee) ; Smrčka, Aleš (advisor)
The goal of this thesis is to create a plugin for application Universal graphic editor, which will allow users to design a hardware architecture. Design of hardware architecture usualy starts with drawing of block diagrams of system which is being developed. Next step is to transcribe this drawn design into some hardware description language (HDL). Since structure of hardware design written in HDL is modular, i.e. similar to the structure of its block diagram, it's possible to translate block diagram of hardware design into HDL source code. The point of this idea is to get rid of designer's work on re-writing the block diagram into HDL language, as this can be automated. Designed plugin allows users to create block diagrams and new hardware components on different layers and switch between these layers interactively. Modul also implements the translation of drawn diagram into VHDL source code.

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