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Acceleration of Data Encryption Algorithms in FPGA
Gajdoš, Miroslav ; Kaštil, Jan (referee) ; Šimek, Václav (advisor)
This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue.
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Hardware Accelerated Encryption of Network Traffic
Novotňák, Jiří ; Kořenek, Jan (referee) ; Žádník, Martin (advisor)
The aim of this thesis is to draft and implement high-speed encryptor of network trafic with throughput 10Gb/s in one way. It has been implementated for FPGA Xilinx Virtex5vlx155t placed on card COMBOv2-LXT. The encryption is based on AES algorithm using 128 bit key length. The security protokol is ESP in version for protokol IPv4. Design is fully synthesizable with tool Xilinx ISE 11.3, however it is not tested on real hardware. Tests in simulation works fine.
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Acceleration of Discrete Optimization Heuristics Using GPU
Pecháček, Václav ; Jaroš, Jiří (referee) ; Pospíchal, Petr (advisor)
Thesis deals with discrete optimization problems. It focusses on faster ways to find good solutions by means of heuristics and parallel processing. Based on ant colony optimization (ACO) algorithm coupled with k-optimization local search approach, it aims at massively parallel computing on graphics processors provided by Nvidia CUDA platform. Well-known travelling salesman problem (TSP) is used as a case study. Solution is based on dividing task into subproblems using tour-based partitioning, parallel processing of distinct parts and their consecutive recombination. Provided parallel code can perform computation more than seventeen times faster than the sequential version.
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Evolutionary Design of Collective Communications Accelerated by GPUs
Tyrala, Radek ; Dvořák, Václav (referee) ; Jaroš, Jiří (advisor)
This thesis provides an analysis of the application for evolutionary scheduling of collective communications. It proposes possible ways to accelerate the application using general purpose computing on graphics processing units (GPU). This work offers a theoretical overview of systems on a chip, collective communications scheduling and more detailed description of evolutionary algorithms. Further, the work provides a description of the GPU architecture and its memory hierarchy using the OpenCL memory model. Based on the profiling, the work defines a concept for parallel execution of the fitness function. Furthermore, an estimation of the possible level of acceleration is presented. The process of implementation is described with a closer insight into the optimization process. Another important point consists in comparison of the original CPU-based solution and the massively parallel GPU version. As the final point, the thesis proposes distribution of the computation among different devices supported by OpenCL standard. In the conclusion are discussed further advantages, constraints and possibilities of acceleration using distribution on heterogenous computing systems.
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Acceleration of Algorithms for Triplex Detection in DNA Sequences
Weiser, Michal ; Lexa, Matej (referee) ; Martínek, Tomáš (advisor)
Triplex forms of DNA act as main factors of some important cell functions. However, their positions within genome and their effect on cell functions are not known well. Triplex search algorithms often don't consider many of triplexs features and the possibility of occurrence of errors. In the other hand the complexity of full featured algorithms is extremely high. This paper shows the way to speed up the algorithm that considers all known triplex features. Parallel aproach allows due to CUDA technology acceleration up to 50.
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Acceleration of Transistor-Level Evolutionary Design of Digital Circuits Using Zynq
Mrázek, Vojtěch ; Sekanina, Lukáš (referee) ; Vašíček, Zdeněk (advisor)
The goal of this project is to design a hardware unit that is designed to accelerate evolutionary design of digital circuits on transistor level. The project is divided to two parts. The first one describes design methods of the MOSFET circuits and issues of evolutionary algorithms. It also analyses current results in this domain and provides a new method for the design and optimization. The second part describes proposed unit that accelerates the new method on the circuit Zynq which integrates ARM processor and programmable logic. The new method functionality has been empirically analysed in the task of optimization of few circuits with more inputs. The hardware unit has been tested for designing of gates on transistor level.
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Acceleration of pedestrians move from a standing start
Ciępka, Piotr ; Reza, Adam ; Zębala, Jakub
The article reports the results of the accelerations of women and men from a standing start to slow, normal and fast walking, running and forcing. The obtained results presented in the form of functions depending on the road in time, compared with the results of tests carried out in 90’s of twenty century by Strouhal, Kuhnel and Hein. There were differences between those results, which allow to apply new data of acceleration.
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Framework for Dynamic Partial Reconfiguration of Virtex-5 FPGA
Raček, Jakub ; Viktorin, Jan (referee) ; Matoušek, Jiří (advisor)
The thesis is focused on design and implementiation of a framework for Dynamic Partial Reconfiguration for FPGA architecture Virtex-5. The aim of the framework is to simplify creating applications with hardware accelerators using Dynamic Partial Reconfiguration. Using this framework, a demonstration application was created for pattern-matching incoming network packets. The process of Dynamic Partial Reconfiguration is controlled by GNU/Linux type operating system, which runs on MicroBlaze processor. This also allows to run less demanding applications and the processing of packets using software.
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Acceleration of Algorithms for Approximate String Matching
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The objective of this bachelor's thesis is to design and implement architecture for FPGA chips that accelerates matching of two strings and scoring them for similarity. Used processes come from bioinformatics algorithms, especially Needleman-Wunsch and Smith-Waterman. Due to general design and generic implementation in VHDL the unit is able to compare any sequences of characters, which is a task widely used in many branches of informatics from database searches (where approximate matching allows discovery of spelling errors) to spam detection. Depending on task specification the acceleration speed up against common software solution can reach orders of hundreds or even thousands.
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