National Repository of Grey Literature 111 records found  1 - 10nextend  jump to record: Search took 0.00 seconds. 
Hardware Acceleration of Encryption Algorithms Using Xilinx Zynq Technology
Linner, Marek ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The main concern of this paper are two world standard encryption algorithms Data Encryption Standard DES (DES for short) and Advanced Encryption Standard (further mentioned as AES). For these two respective algorithms, three publicly available implementations are integrated into a benchmarking code in C programming language. The code has been executed, implementations measured with three different input block lengths and bitrate calculated for each implementation. The thesis also includes hardware implementation of both encryption algorithms DES and AES using VHDL language, simulation of the synthesised circuits and calculation of the hardware implementations' bitrate using Vivado simulator's timing reports. These measured bitrates are then compared with the bitrates of benchmarked software implementations. Paper includes all source codes of the benchmarking C program and VHDL implementation, along with program written in C# used to generate VHDL components and another C# program used for automated testing. 
Implementation of Encryption Algorithms in VHDL Language
Fruněk, Lukáš ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The thesis deals with the design and implementation of the encryption algorithms DES and AES, operating in the CTR mode. The designed modules are implemented in the VHDL language and are mapped in the FPGA Intel Arria 10 SX 480. Algorithms are optimized for maximum throughput using loop unrolling and inner pipelining. The encryption module for DES reaches throughput of 26.2 Gbit/s with the circuit operating 410 MHz, and the module for AES reaches throughput of 34.6 Gbit/s with the circuit operating at 271 MHz. The reached throughput is in the order of thousand times faster than of the same encryption algorithms implemented in software for built-in microprocessors.
Anomaly Detection in IoT Networks
Halaj, Jozef ; Hujňák, Ondřej (referee) ; Kořenek, Jan (advisor)
The goal of the thesis was an analysis of IoT communication protocols, their vulnerabilities and the creation of a suitable anomaly detector. It must be possible to run the detector on routers with the OpenWRT system. To create the final solution, it was necessary to analyze the communication protocols BLE and Z-Wave with a focus on their security and vulnerabilities. Furthermore, it was necessary to analyze the possibilities of anomaly detection, design and implement the detection system. The result is a modular detection system based on the NEMEA framework. The detection system is able to detect re-pairing of BLE devices representing a potential pairing attack. The system allows interception of Z-Wave communication using SDR, detection of Z-Wave network scanning and several attacks on network routing. The system extends the existing detector over IoT statistical data with more detailed statistics with a broader view of the network. The original solution had only Z-Wave statistics with a limited view of the network obtained from the Z-Wave controller. The modular solution of the system provides deployment flexibility and easy system scalability. The functionality of the solution was verified by experiments and a set of automated tests. The system was also successfully tested on a router with OpenWRT and in the real world enviroment. The results of the thesis were used within the SIoT project.
Integration of New Wireless Technologies and Devices into the BeeeOn Gateway
Bednařík, David ; Korček, Pavol (referee) ; Kořenek, Jan (advisor)
This master thesis deals with the integration of new devices from the manufacturers Revogi, Tabu Lumen, Sonoff and HomeMatic into the BeeeOn Gateway software. The theoretical part deals with the architecture of the BeeeOn Gateway software and describes the characteristics, behavior and way of communication with devices from the above mentioned manufacturers. This part of thesis also contains a description of the communication technologies used by these devices. They include Bluetooth Low Energy, the WiFi and the 868 MHz radio. The practical part mentions the way of extension of BeeeOn Gateway software to modules that implement support for smart devices. This section also describes how the correctness of implementation was verified and testing of the entire BeeeOn Gateway software. The testing of gateway is performed by unit and integration tests, which verify the behavior of individual gateway components as well as the whole gateway.
Processing Unit for Analysis and Modification of Network Traffic
Pazdera, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This paper deals with the design and implementation of the Processing Unit for Analysis and Modification of Network Traffic. The proposed unit is intended to analyse an incoming network traffic and perform packet header editations to provide the proper packet delivery. The designed architecture has the following characteristics. It is based on the stream processor concept which allows to process independent stream elements (i.e. packets) in parallel. Multiply stream clients can be used to process the same stream data concurrently. The stream clients can be driven either autonomously or by program. The packets are processed according to the incoming metadata and transmited to the output. The Processing Unit has been implemented in VHDL language. The target technology is Field Programmable Gate Array (FPGA).
Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
Implementation of Communication Middleware in JAVA ME
Martinák, Jan ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
In almost each enterprise there is a software support for business processes. With a growing number of the applications there is an increasing demand to integrate those applications in order to have an effectively working environment, which generates profit. In enterprise applications integration there are few principles, each with their own advantages and disadvantages. However, the message-oriented middleware layer proves to be the best solution to many integration scenarios. This work deals with an enterprise of applications running on multifunction embedded office devices based on Java ME platform, and introduces an in-house developed communication middleware layer to integrate those applications. The resulting software component applies principles of messaging in a printing management SOA environment to communicate with a print server using a designed set of messages.
DMA Controller and Network Interface Card Driver for COMBO2 Platform
Kaštovský, Petr ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
There is a family of COMBO cards used for netork monitoring acceleration being developed on the Liberouter project, which is the CESNET's research activity. These cards are equipped with Xilinx's programmable field array. To enable usage of classic tools for network monitoring and management, not only application specific tools, it is necessary to implement network interface card on the platform, that realizes packet reception and transmission through the standard Linux kernel interface. This thesis describes the design and implementation of network interface card's key components. Those are DMA controller and Linux device driver.
Platform for Rapid Development of Network Devices
Tobola, Jiří ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis deals with the design and implementation of an FPGA-based platform for rapid development of network applications for the COMBO cards family. The proposed platform includes a generic data transfer protocol - FrameLink, a set of tools for FrameLink manipulation, network interface blocks for 1 Gigabit Ethernet, high-speed connection to the software layer via PCI, PCI-X or PCI Express bus and a set of IP cores for network traffic analysis and processing. The benefits of the proposed platform are demonstrated on design and implementation of a network interface card, hardware firewall and exporter of unified packet headers.
Hardware Acceleration of Image Filtering
Fiala, Martin ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This master's thesis contains introduction to image filtration problems, especially to theoretical outlets, whose origin lies in linear systems theory and mathematical function analysis. There are described some approaches and methods which are used to image smoothing and for edge detection in an image. Mainly Sobel operator, Laplace operator and median filter are covered. The main contents of this project is discussion of some approaches of hardware acceleration of image filtering and design of time effective software and hardware implementations of filters in a form of program functions and combinational circuits using theoretical knowledges about time complexity of algorithms. Hardware and software implementation of named filters was done too. For every filter, time of filtration was measured and results were compared and analyzed.

National Repository of Grey Literature : 111 records found   1 - 10nextend  jump to record:
See also: similar author names
1 Korenek, Jozef
1 Kořenek, Jakub
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