Original title: Framework pro částečnou dynamickou rekonfiguraci FPGA Virtex-5
Translated title: Framework for Dynamic Partial Reconfiguration of Virtex-5 FPGA
Authors: Raček, Jakub ; Viktorin, Jan (referee) ; Matoušek, Jiří (advisor)
Document type: Bachelor's theses
Year: 2014
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Abstract: [cze] [eng]

Keywords: acceleration; Dynamic Partial Reconfiguration; FPGA; framework; Virtex-5; akcelerace; FPGA; framework; Virtex-5; částečná dynamická rekonfigurace

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/53055

Permalink: http://www.nusl.cz/ntk/nusl-235813


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses
 Record created 2016-06-03, last modified 2022-09-04


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