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Automatization of Analysis of Performance and Power Consumption
Rudolf, Tomáš ; Jaroš, Jiří (referee) ; Nikl, Vojtěch (advisor)
This thesis deals with increasing efficiency of supercomputers. Higher efficiency can be achieved by reducing frequency of processor if the algorithm does not slow down significantly. This thesis presents set of scripts designed to monitor consumption of processor along with scripts that visualize these measured values. It also allows easy control of processor frequency. The created solution gives user a capability to measure given algorithm efficiency and optimize computing power of specific computer exactly for the algorithm. Due to this work the user will be informed about whether it is advantageous to run his algorithm on one or other frequency of the processor.
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Implementation of a Boot Controller for Intel FPGAs
Hak, Tomáš ; Fukač, Tomáš (referee) ; Matoušek, Jiří (advisor)
This thesis touches the topic of using FPGA technology in the field of computer networks, specifically for hardware acceleration of network traffic processing on a network card developed by the CESNET association. FPGA technology is popular mainly due to the possibility to easily reconfigure the chip and fix any errors or update the firmware. The thesis first discusses the design and implementation of a new unit for Intel FPGA, which will be able to communicate with the external configuration flash memory of the chip featured on the card mentioned above. It then goes on to address the design and implementation of a software tool that will allow, via the newly implemented firmware unit, to load new configuration data into the flash memory and force reconfiguration of the FPGA chip using this newly loaded data. Towards the end of the thesis, the functionality of the newly implemented system is tested in practice.
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Performance Analysis of IBM POWER8 Processors
Jelen, Jakub ; Kešner, Filip (referee) ; Jaroš, Jiří (advisor)
This paper describes the IBM Power8 system in comparison to the Intel Xeon processors, widely used in today’s solutions. The performance is not evaluated only on the whole system level but also on the level of threads, cores and a memory. Different metrics are demonstrated on typical optimized algorithms. The benchmarked Power8 processor provides extremely fast memory providing sustainable bandwidth up to 145 GB/s between main memory and processor, which Intel is unable to compete. Computation power is comparable (Matrix multiplication) or worse (N-body simulation, division, more complex algorithms) in comparison with current Intel Haswell-EP. The IBM Power8 is able to compete Intel processors these days and it will be interesting to observe the future generation of Power9 and its performance in comparison to current and future Intel processors.
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Intel Integrated Performance Primitives and their use in application development
Machač, Jiří ; Přinosil, Jiří (referee) ; Malý, Jan (advisor)
The aim of the presented work is to demonstrate and evaluate the contribution of computing system SIMD especially units MMX, SSE, SSE2, SSE3, SSSE3 and SSE4 from Intel company, by creation of demostrating applications with using Intel Integrated Performance Primitives library. At first, possibilities of SIMD programming using intrinsic function, vektorization and libraries Intel Integrated Performance Primitives are presented, as next are descibed options of evaluation of particular algorithms. Finally procedure of programing by using Intel Integrated Performance Primitives library are ilustrated.
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General Processing on Graphics Processing Units for Industrial Systems
Lukačovič, Martin ; Mašek, Jan (referee) ; Krkoš, Radko (advisor)
The thesis deals with the abilities of graphics processors for GPGPU. It contains historical solutions to contemporary design. There are also described graphics processors from the largest manufacturers of this time, their focus and goals in the future. For algorithms implementation using GPU, there are necessary APIs that offer various possibilities of execution. In addition to the CPU and GPU universal heterogeneous computing, there are alternatives such as FPGA and DSP so it is necessary to consider the price and energy cost. Part of the work is devoted to the communication possibilities with the hardware and advanced memory approaches. For demonstrating parallel computing an implementation of matrix multiplication in OpenCL was realized.
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Processing units of last generation processors and their utilization
Šlenker, Samuel ; Pavlíček, Tomáš (referee) ; Balík, Miroslav (advisor)
The aim of this thesis was to study and subsequently process the differences between the older instruction sets and newer instruction sets, to specify the benefits of the individual extensions, to compare the way of computations of the individual SIMD processing units and to compare the implementation of these processing units in Intel and AMD companies. Part of this work are two theoretical introductions to laboratory tasks.
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Samples of examples for configurable gate array
Bajer, Jan ; Spáčil, Tomáš (referee) ; Bastl, Michal (advisor)
This thesis introduces the issue of configurable gate arrays and their position with respect to microprocessor technology. The aim is to present work with gate arrays on a set of basic realizations within the field of mechatronics. The examples are processed using VHDL and they are primarily intended for Altera / Intel devices.
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Implementation of Digital Circuit for High-Speed Network Communication in FPGA
Kondys, Daniel ; Cíbik, Peter (referee) ; Smékal, David (advisor)
Vysokorychlostní síťové karty často obsahují prvky pro hardwarovou akceleraci, která jim umožní efektivně zpracovávat data i při velmi vysokých rychlostech. Tato práce se zabývá tvorbou digitálního obvodu pro FPGA, který bude přenášet Ethernetové rámce rychlostí až 400 Gb/s. K tomu využívá bloky duševního vlastnictví pro Ethernet, které jsou součástí moderních FPGA čipů od firmy Intel. Jedná se o FPGA Stratix 10, které obsahuje bloky duševního vlastnictví typu E-tile, a Agilex, které obsahuje bloky duševního vlastnictví typu F-tile. Před vlastním návrhem se práce zabývá teoretickým rozborem standardu Ethernet a činnostmi jednotlivých podvrstev, popisuje vybrané FPGA čipy a zabývá se i NDK platformou, do níž bude vytvořený obvod zapojen. Praktická část spočívá v konfiguraci daných duševních bloků pro Ethernet a jejich integrací do vytvářeného obvodu. Nakonec jsou popsány metody pro ověření funkčnosti vytvořeného obvodu. Ty zahrnují verifikaci a testy na platformách s danými FPGA čipy. Výsledky ukazují, že vytvořený obvod je funkční a dosahuje rychlosti i 400 Gb/s. Jeho využití spočívá zejména v poskytnutí komunikace přes Ethernet pro digitální obvod, který bude dodáván jako součást firmwaru pro síťovou kartu XpressSX AGI-FH400G vyvinutou sdružením CESNET z.s.p.o a společností REFLEX CES.
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FPGA Digital Circuit for up to 400 Gbps Transfers over Ethernet
Kondys, D. ; Smékal, D.
Network cards with a hardware acceleration feature are a popular solution for meeting the ever-increasing demands for throughput in high-speed networks. Utilizing the FPGA (Field Programmable Gate Array) chips as the hardware acceleration elements, this paper presents a generic and highly modular digital circuit for FPGA that manages the transfer of data in form of Ethernet frames at rates reaching up to 400 Gbps. To achieve this, the proposed digital circuit takes advantage of the Ethernet intellectual property (IP) blocks in high-end FPGAs from Intel. By first implementing and fine-tuning it for data rates up to 100 Gbps, the next step is expanding it to reach data rates up to 400 Gbps. The created digital circuit will then be used in the FPGA design for the XpressSX AGI-FH400G network card (among others) created by companies CESNET a.l.e and REFLEX CES. Even though the target data rate is 400 Gbps, this paper focuses on the first step, which is the utilization of the Intel Ethernet hard IP blocks to reach 100 Gbps.
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