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Portable Stimulus Scenarios Specification for RISC-V Processor Modules
Bardonek, Petr ; Bidlo, Michal (referee) ; Zachariášová, Marcela (advisor)
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.
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RISC-V Processor Peripherals
Vavro, Tomáš ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
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Graphical Simulator of Superscalar Processors
Vávra, Jan ; Mrázek, Vojtěch (referee) ; Jaroš, Jiří (advisor)
Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.
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Framework for RISC-V Compliance Tests Execution
Skála, Milan ; Čekan, Ondřej (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.
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RISC-V Processor Model
Barták, Jiří ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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RISC-V microprocessor implementation with bit manipulations instruction set extension
Chovančíková, Lucie ; Bohrn, Marek (referee) ; Pristach, Marián (advisor)
This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.
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Generation of Object Files for RISC-V
Benna, Filip ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This master’s thesis deals with the topic of program source code compilation for RISC-V processor architecture. The generated object files need to be compatible with GNU binutils open source tools which are already available for the architecture. The focus is on relocations which must be correctly detected in Codasip Studio tools and transformed into RISC-V platform specific relocation types.
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Formal verification of RISC-V processor with Questa PropCheck
Javor, Adrián ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.
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RISC-V Model Creation
Nosterský, Milan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.
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Enriching the Process of Verification of RISC-V Processor with Formal Techniques
Horký, Jakub ; Šnobl, Pavel (referee) ; Hruška, Tomáš (advisor)
This thesis provides a brief overview of the RISC-V architecture, design of processors, and how easily a bug can arise during the development. Then this thesis describes the way functional verification tries to discover those bugs and what are its pros and cons. More specifically, the thesis focuses on what the verification environment in UVM look like. Then the thesis describes, how formal verification fits in to the functional verification and shows the tools that are available for formal verification. The final part of this thesis, describes the process of how I wrote the assertions (written in SVA) for a RISC-V processor, using a property checking tool. Using these assertions for verifying a processor in the late stage of development, when functional verification already had the possibility to discover most of the bugs, I still was able to discover few of those bugs.
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