|
|
Automatic project code generation in TIA portal
Halata, Roman ; Jirgl, Miroslav (referee) ; Štohl, Radek (advisor)
The diploma thesis deals with an automatic code generation for PLC from Siemens. The first part focuses on currently available tools for code generation and options of C# library Siemens TIA Openness. Furthermore, a design for the project structure in the TIA portal is created. Finally, a user application for automatic code generation in TIA portal v15 is designed and created, especially suitable for larger projects that could be divided into individual stations.
|
|
|
Information System Generating
Voborník, Petr ; Jirák, Ota (referee) ; Ruttkay, Ladislav (advisor)
The work sets out requirements for the implementation of information systems generator. It deals with finding common elements of information systems. Further it specifies requirements for registration of a conceptual model. Then it goes on to describe user's general point of view of systems. Implementation technologies are chosen and architecture of generated systems is designed based on mentioned analysis. Generated systems are designed to provide basic operations for working with items of the system. Moreover, different ways of generating code are discussed. Metamodel of conceptual model is designed and its possible types of representation are discussed. At the end problems which generator deals with are described.
|
|
|
Novel Methods of Control Systems Design with MATLAB/Simulink
Válek, Vít ; Kozovský, Matúš (referee) ; Blaha, Petr (advisor)
The content of this thesis is to introduce the tools of MATLAB/Simulink, which allow to generate the source code in C language. It will be demonstrated how to combine the source code written in C with Simulink model and MATLAB code. The code will be generated for the selected functions and compared with RTCESL library functions. In the last part of this thesis the principle of FOC will be briefly described. For a simplified loop of FOC, the code will be generated and then compared with handwritten code. For comparison, the microcontroller KV46F256 from NXP Semiconductors is used.
|
|
|
Octave to C++ Source-to-Source Compiler
Ševčík, Václav ; Křivka, Zbyněk (referee) ; Kolář, Martin (advisor)
It is difficult to use programs developed in the interactive programming environment Matlab for low-memory devices and for integration into projects without the language support. Therefore, the programs are converted into C++. In practice, manual transfer is used which significantly prolongs the time of the developing program. The work focuses on the automation of translation from Octave/Matlab to C++ using the Eigen library to enable matrix and vector operations. The translator allows 39 basic operations and 13 functions of the Octave language. Experiments show that this translation will reduce memory requirements of up to 99%
|
|
|
Model Driven Development of Android Applications
Bělehrádek, Stanislav ; Burget, Radek (referee) ; Rychlý, Marek (advisor)
This thesis deals with the design and implementation of Android application development tool based on model driven software development. The first part of the thesis is focused on general software development and next part on software development based on model driven development and executable UML. In next part Android platform, methods of Android application development and existing MDD tools are described. This thesis continues with the design of my own MDD tool for the creation of Android applications. The designed tool is realized like Gradle plugin and independent development environment using thisplugin. The designed tool is based on fUML and ALF language. The features and options of development tool are demonstrated by creation of example application.
|
|
|
SIMD code generator
Tuček, Karel ; Bednárek, David (advisor) ; Arcaini, Paolo (referee)
Title: SIMD code generator Author: Karel Tuček Department: Department of Software Engineering Supervisor: RNDr. David Bednárek, Ph.D., Department of Software Engineering Abstract: The center of our interest is a problem of pipelined realisation of a special case of data processing networks. These realisations are supposed to realise some computations on series of independent data sets while utilizing SIMD instructions. The aim of this paper is to theoretically investigate the possibilities and the problems of employment of control flow in these networks and also to implement a general framework suitable for generation of these realisations. The main idea is utilisation of an algorithm crawling over partitions of a network factorised with respect to its control flow. Our idea is that SIMD parallelism should take place on the same instruction realised across multiple data sets. We illustrate the problems relevant to employment of branching and loops in these networks. We especially discuss a problem of data ordering and also provide relevant proofs. In the analytical part, we show implementation of a general framework which we believe to be suitable for processing of these networks. We also provide examples utilising Intel's SIMD Streaming Extensions. Keywords: Processing networks SIMD Parallelism iii
|
|
|
.NET library for the MediaWiki API
Onderka, Petr ; Petříček, Tomáš (advisor) ; Pokorný, Jaroslav (referee)
.NET library for the MediaWiki API Abstract: MediaWiki wikis provide their users an API, that can used to programmatically access the wiki. This API is large, changes frequently and can be different from wiki to wiki, so it can be a challenge to write a library for accessing the API. This thesis describes LinqToWiki, a library that can be used to access the Me- diaWiki API from C# or other .NET languages. Thanks to the use of LINQ and code generation through Roslyn, code written using this library is readable, discoverable, strongly-typed and flexible.
|
|
|
Code Generation from UML State Machine Description
Píš, Ľuboš ; Richta, Karel (advisor) ; Nečaský, Martin (referee)
This paper discusses the implementation of a suitable algorithm for code generation from UML state machine diagrams. The work includes analysis of state machines described in UML, followed by a description of the input fi le format of the proposed design of the generator and the generator itself. The generator was fully implemented in the work along with other functional requirements. At the end of this thesis is a description of the resulting implementation.
|
|
|
Pattern matching in compilers
Bílka, Ondřej ; Hubička, Jan (advisor) ; Mareš, Martin (referee)
Title: Pattern matching in compilers Author: Ondřej Bílka Department: Department of Applied Mathematics Supervisor: Jan Hubička, Department of Applied Mathematics Abstract: In this thesis we develop tools for effective and flexible pattern matching. We introduce a new pattern matching system called amethyst. Amethyst is not only a generator of parsers of programming languages, but can also serve as an alternative to tools for matching regular expressions. Our framework also produces dynamic parsers. Its intended use is in the context of IDE (accurate syntax highlighting and error detection on the fly). Amethyst offers pattern matching of general data structures. This makes it a useful tool for implement- ing compiler optimizations such as constant folding, instruction scheduling, and dataflow analysis in general. The parsers produced are essentially top-down parsers. Linear time complexity is obtained by introducing the novel notion of structured grammars and reg- ularized regular expressions. Amethyst uses techniques known from compiler optimizations to produce effective parsers. Keywords: Packrat parsing, dynamic parsing, structured grammars, functional programming 1
|
|
|
Generated Peephole Optimizations in LLVM Compiler
Melo, Stanislav ; Podivínský, Jakub (referee) ; Hruška, Tomáš (advisor)
One of the important feature of application specific processors is performance. To maximize it, the compiler must adapt to needs of processor that it is going to compile for and it must generate the most efficient code. One of the ways to do that is to search for appropriate instructions that can be implemented as one instruction with multiple outputs. Afterwards the generated code can be parsed through peephole optimizations that search for instruction patterns and replace them with other instructions to make code more effective. This paper describes the problem of finding and selecting suitable candidates for multiple output instructions. It also provides a brief overview of the few best known algorithms that solve this problem. Eventually it examines possibilities of incorporating this optimizations to LLVM compiler.
|
guest ::
