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Transformation of a Processor Description in CodAL to SystemC Structures
Ondruš, Tomáš ; Hynek, Jiří (referee) ; Přikryl, Zdeněk (advisor)
The goal of this thesis is to create a generator of simulators and hardware representation of application specific processors in a SystemC language. An aim of the first part is to create a wrapper layer compatible with SystemC TLM 2.0 that wraps an existing simulator to avail modeling of transaction oriented systems. The second part is a generator of a hardware representation for the processor that is suitable not only for logical synthesis, but also for the simulation on a cycle accurate level. A final result is a state of the art solution comparable to existing generators.
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Processor Model Creation Using ADL Language
Ostatník, Kristián ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The goal of this thesis is to create an instruction-accurate model of ARC processor using the CodAL ADL language. The first part is dedicated to classification of processors and ADL languages. The second part describes the implementation process and the generation of C/C++ compiler for debugging and verification of the created model. At the end the created model is compared to an existing model ARC 700 on a set of benchmark tests.
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Architecture Information for LLVM Compiler Optimizations
Svoboda, Jan ; Dolíhal, Luděk (referee) ; Hruška, Tomáš (advisor)
Tato práce se zabývá automatickou extrakcí informací o architektuře procesoru z jazyka CodAL. Získané informace jsou využity jako základ pro cenový model optimalizátoru překladače LLVM. V rámci práce vznikl nový systém, který vytváří cenový model, převádí jej do C++ kódu a sestavuje do dynamické knihovny. Tato knihovna je za běhu načtena překladačem a využita pro přesnější rozhodování o přínosech jednotlivých optimalizací. Výsledkem práce je průměrné 14% snížení velikosti strojového kódu programů a až 68% zlepšení výkonu generovaného kódu.
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Advanced Techniques of C-to-HDL Tranformations
Michalik, Martin ; Křoustek, Jakub (referee) ; Přikryl, Zdeněk (advisor)
This thesis deals with proposal and implementation of advanced transformations used du- ring generation HDL from behavior description written in C language, which is part of architecture specification in CodAL language. These transformations focus either on the reduction of time required for execution, increasing frequency or area reduction of target hardware. This thesis discusses main problems of C to HDL transformation and describes principles and analysis of proposed transformations. Transformations results are discussed based on the visualisation of control data flow and register transfer level graphs, simulation of generated VHDL source files in the ModelSim software and synthesis of these source files for target FPGA Vertix 5 in the Xilinx ISE software.
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Instruction level parallelism in modern processors
Sláma, Pavel ; Levek, Vladimír (referee) ; Pristach, Marián (advisor)
Basic methodology that exploits instruction level parallelism is called pipelining and it is part of every processor for decades. The ideal pipeline increases performance and efficiency for a relatively small cost. But the real pipeline has number of limitations caused by dependencies and hazards between instructions. The aim of this thesis is to discuss techniques used to improve efficency and performance of pipelined processors, to implement selected techniques to a RISC processor model and discuss its benefits.
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RISC-V microprocessor implementation with bit manipulations instruction set extension
Chovančíková, Lucie ; Bohrn, Marek (referee) ; Pristach, Marián (advisor)
This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.
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CodAL Language Editor in Eclipse Framework
Hynek, Jiří ; Dolíhal, Luděk (referee) ; Přikryl, Zdeněk (advisor)
The Master thesis is focused on creation of an editor of CodAL language for the development toolkit of the project Lissom which is based on Eclipse framework. The goal of this thesis is to analyze the problem of editor creation and the features in existing editors which add some value to their usability. The outline of parser creation and subsequent code analysis of the source codes written into the editor is described in the theoretical part. It also explains the syntax and semantic aspects of the CodAL language. In the practical part the new CodAL language editor is designed and developed. The new CodAL language editor integrated into the development toolkit of the project Lissom is the final outcome of this thesis.
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AVR32 Model Coreation
Sarčák, Rostislav ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
This barchelor's thesis describe creation of AVR32 processor instruction-accurate model using CodAL language. In this thesis RISC AVR32 architecture, approach to implementation of the model, testing and generating of software toolchain is described. Model development is realized in Codasip framework. Model contains implementation of AVR32 instruction set. The result of this work is AVR32 processor instruction-accurate model.
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Modelling of PowerPC Processor
Blaha, Hynek ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Processor architectures are becoming increasingly complex, so great emphasis is put on the automation of their desings. This bachelor thesis describes the design of the PowerPC processor architecture in Codal language. The model is created according to avaliable documentation. The functionality and efficiency of the model was verified by tests provided by research group Lissom and compared to current competitor.
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Compilation of C++ Applications for Embedded Devices
Nosterský, Milan ; Přikryl, Zdeněk (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the integrations of C++ programming language and its standard C++11 into the compiler for embedded systems. This compiler is based on LLVM project and it is generated from Codasip Studio. Codasip Studio is tool for design of the aplication specific processor cores, it is also allows generate compiler, which is based on the description of semantics section in processor's instruction set for any target processor architecture. C++ is programming language based on the C, which is extended by object oriented design and many other features. C++ language allows writing of very effective code on high level of abstraction. Funcionality of implementation is tested on testsuite in last phase of master's thesis.
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