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Transformation between the Microprocessor's Description Language and the Hardware Language
Novotný, Tomáš ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.
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RISC-V microprocessor implementation with bit manipulations instruction set extension
Chovančíková, Lucie ; Bohrn, Marek (referee) ; Pristach, Marián (advisor)
This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.
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Simulation of the 8051 Microprocessor Architecture
Šimon, Petr ; Křoustek, Jakub (referee) ; Hruška, Tomáš (advisor)
More than 90% of processors are used in embedded systems today. Processor design for embedded systems is becoming complicated, so it should be automate as much as possible. This bachelor thesis deals with design of the microcontroller 8051. Design is created according to available documentation and ISAC language is used for model description. Results of model simulations are analyzed at the end of this thesis.
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Automated Testing in FPGA
Valecký, David ; Přikryl, Zdeněk (referee) ; Hruška, Tomáš (advisor)
The aim of this work is to analyze the testing of processors developed by Codasip and find out which of the tests should be performed using FPGA devices. Furthermore, the goal is to design and implement a system for remote operation of FPGA devices connected to a central server in order to perform tests. The system is programmed in Python using the client-server architecture and Flask framework. The interaction of the server with the FPGA devices is ensured with the help of OpenOCD. The implemented system allows a~user to find out the status of connected FPGA circuits, configure these devices and then use them to run tests. The work uses FPGAs Artix-7 series made by Xilinx, placed on Digilent Nexys A7 development boards. The resulting testing of programmed chips in an FPGA representing a microprocessor is accelerated when using an FPGA device. Its results are faster on hardware representation than on its simulation in some cases.
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Overclocking of Modern Processors with an Emphasis on Performance, Power Consumption and Temperature
Kelečéni, Jakub ; Vaverka, Filip (referee) ; Nikl, Vojtěch (advisor)
This thesis analyzes the dependency of performance, power consumption and temperature on processor frequency. Theoretical part discusses the processor architecture, benchmarks and algorithm types. Experimental part is focused on benchmarks - matrix multiplication, Quicksort, PI number calculation, Ackermann function, LAMMPS, PMBW, Linpack. This set of benchmarks includes both single-threaded and multi-threaded algorithms. Testing consist of three different settings of processor frequency. Multi-threaded benchmarks using different number of threads. Informations regarding the power consumption of CPU and RAM were recorded during these tests. Every test logs his running time. The impact of parallelization on power consumption and runtime is also reflected. Results from the tests are shown in charts and tables. The proper configuration of CPU for each given algorithm is analyzed in conclusion.
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Connecting external devices with Freescale MC9S08LH64 microcontroller by IIC and SPI bus
Pamánek, David ; Holek, Radovan (referee) ; Macho, Tomáš (advisor)
The content of this thesis is to introduce the SPI and IIC serial buses, their properties and description of their function. After this part there is the description of the microcontroller Freescale MC9S08LH. It gives the basic description of whole device and more detailed description of SPI and IIC modules. In the next part of the document there is described four external devices, which I have chosen. For each device there is shown connetion diagram and printed circuit board. In the end of this document is description of libraries created for communication between chosen devices and microcontroller.
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MicroBlaze processor implementation using CodAL language
Hájek, Radek ; Zachariášová, Marcela (referee) ; Pristach, Marián (advisor)
The diploma thesis contains theoretical basis, classification and function of processors. It summarizes the principle of pipelined instruction processing and the types of hazards in the microarchitecture of the processor. It also introduces design of processors using CodAL language developed by Codasip company. In the practical part of the thesis the model of MicroBlaze core developed by Xilinx company was described in the CodAL language. Designed model was tested and implemented into the FPGA device as practical example.
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NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
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Smart Wearable
Moravec, Luboš ; Macháň, Ladislav (referee) ; Šteffan, Pavel (advisor)
This master’s thesis deals with the explanation of the concept of smart wearables and the different application possibilities. This work also includes examples of finished demonstration devices in this category. Part of this work is devoted to guide the selection of appropriate components for the design of new equipment in the category of smart wearable. The result of this thesis is designed wearable and charging station. This device is able to read user input and display that information on a smart device running under Android system connected via Bluetooth technology.
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