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Processor Pineapple One
Szkandera, Filip
This thesis deals with the design, simulation and making of a RISC-V based processoronly out of descrete logic components. The final product is a macrocontroller that integrates a processor,program memory, data memory, graphics card and an input-output ports in a tower structuremade of nine circuit boards. This thesis also describes a simple shell application programmed in a Clanguage, that runs natively on this device.
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RISC-V Processor Peripherals
Vavro, Tomáš ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
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Graphical Simulator of Superscalar Processors
Vávra, Jan ; Mrázek, Vojtěch (referee) ; Jaroš, Jiří (advisor)
Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.
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RISC-V microprocessor implementation with bit manipulations instruction set extension
Chovančíková, Lucie ; Bohrn, Marek (referee) ; Pristach, Marián (advisor)
This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.
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Formal verification of RISC-V processor with Questa PropCheck
Javor, Adrián ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.
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Specialized Instruction Design
Koscielniak, Jan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The purpose of this thesis is to design and implement specialized instructions for RISC-V instruction set architecture. These instruction are used to accelerate a set of selected cryptographic algorithms. New instructions are implemented in Codasip Studio for 32bit processor model with RV32IM instruction set. Open source implementations were selected and edited to use new instructions. Instructions were used on respective algorithms, tested and profiled. The outcome of this thesis is instruction set extension, that enables up to seven times speed up, depending on used algorithm.
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Framework for RISC-V Compliance Tests Execution
Skála, Milan ; Čekan, Ondřej (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.
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Portable Stimulus Scenarios Specification for RISC-V Processor Modules
Bardonek, Petr ; Bidlo, Michal (referee) ; Zachariášová, Marcela (advisor)
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.
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Generation of Object Files for RISC-V
Benna, Filip ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This master’s thesis deals with the topic of program source code compilation for RISC-V processor architecture. The generated object files need to be compatible with GNU binutils open source tools which are already available for the architecture. The focus is on relocations which must be correctly detected in Codasip Studio tools and transformed into RISC-V platform specific relocation types.
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RISC-V Model Creation
Nosterský, Milan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.
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