Original title: Formalní verifikace RISC-V procesoru s využitím Questa PropCheck
Translated title: Formal verification of RISC-V processor with Questa PropCheck
Authors: Javor, Adrián ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
Document type: Master’s theses
Year: 2020
Language: slo
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [slo] [eng]

Keywords: Formal verification; model checking; Questa PropCheck; RISC-V; SystemVerilog assertions

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/189360

Permalink: http://www.nusl.cz/ntk/nusl-413219


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2020-07-11, last modified 2022-09-04


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