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Dynamic analysis of lightweight bridge construction
Krzywoň, Filip ; Nevařil, Aleš (referee) ; Vlk, Zbyněk (advisor)
The thesis compares the dynamic response of lightweight footbridge structure. Two finite element models were made. One in Ansys 15.0 software, and another in RFEM 5.05 structural software. The results of the models were compared to each other. The response to dynamic excitation from pedestrians was evaluated in accordance to ČSN EN 1990/A2.
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GPU Image Processing Library
Čermák, Michal ; Španěl, Michal (referee) ; Smrž, Pavel (advisor)
This work is concerned with architecture of recent Nvidia graphics cards and application programming interface CUDA. That is used to create accelerated image processing library. It place emphasis on testing performance gain compassion with high optimized and used OpenCv library.
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Compiler for EdkDSP Platform
Baručák, Robert ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Goal of this bachelor's thesis was to create a compiler system for EdkDSP platform. Two different approaches to construction of compiler system for multiprocessor platform are presented. Compiler is based on LLVM compiler infrastructure. As a result, two versions of compiler system utilising hardware capabilities of EdkDSP were created. Developed solutions have a few constraints which are discussed in this paper.
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Acceleration of Neural Networks in FPGA
Krčma, Martin ; Vašíček, Zdeněk (referee) ; Kaštil, Jan (advisor)
This thesis deals with an acceleration of neural networks, which are implemented into the fi eld programmable gate arrays. Two di fferent hardware implementation are presented and compared with each other and confronted with the software implementation. The tools for easy implementation of neural networks in FPGAs are introduced.
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Accelaration of RSA on GPUs
Balogh, Tomáš ; Jaroš, Jiří (referee) ; Vašíček, Zdeněk (advisor)
This bachelor's thesis discusses implementation of RSA algorithm using Montgomery multiplication for graphic cards. There are four versions of implementation created for CUDA platform with aim to achieve as high computation acceleration as possible compared to processor computation. Acceleration of computation is among other things achieved by parallelization of arithmetic operations addition and multiplication of large numbers.
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Cartesian Genetic Programming in Python
Dvořáček, Petr ; Bidlo, Michal (referee) ; Vašíček, Zdeněk (advisor)
Cartesian genetic programming (CGP) is one of the evolutionary methods. It was created for electronic circuit design. It can be used also in optimization of functions, classification, evolutionary art etc. This paper describes acceleration techniques to speed up the evaluation of candidate solution in CGP in Python.
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Hardware Acceleration of Cipher Attack
Okuliar, Adam ; Slaný, Karel (referee) ; Vašíček, Zdeněk (advisor)
Hardware acceleration is often good tool to achieve significantly better performance of processing great ammount of data or of realization of parallel algoritms. Aim of this work is to demonstrate resoluts of using FPGA circuits for implementation exponentially complex algorithm. As example haschosen brute-force attack on WEP cryptographic algorithm with 40-bit long key. Goal of this work is to compare properties and performance of software and hardware implementation of choosen algorithm.
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Acceleration of Data Encryption Algorithms in FPGA
Gajdoš, Miroslav ; Kaštil, Jan (referee) ; Šimek, Václav (advisor)
This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue.
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Hardware Accelerated Encryption of Network Traffic
Novotňák, Jiří ; Kořenek, Jan (referee) ; Žádník, Martin (advisor)
The aim of this thesis is to draft and implement high-speed encryptor of network trafic with throughput 10Gb/s in one way. It has been implementated for FPGA Xilinx Virtex5vlx155t placed on card COMBOv2-LXT. The encryption is based on AES algorithm using 128 bit key length. The security protokol is ESP in version for protokol IPv4. Design is fully synthesizable with tool Xilinx ISE 11.3, however it is not tested on real hardware. Tests in simulation works fine.
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Acceleration of Discrete Optimization Heuristics Using GPU
Pecháček, Václav ; Jaroš, Jiří (referee) ; Pospíchal, Petr (advisor)
Thesis deals with discrete optimization problems. It focusses on faster ways to find good solutions by means of heuristics and parallel processing. Based on ant colony optimization (ACO) algorithm coupled with k-optimization local search approach, it aims at massively parallel computing on graphics processors provided by Nvidia CUDA platform. Well-known travelling salesman problem (TSP) is used as a case study. Solution is based on dividing task into subproblems using tour-based partitioning, parallel processing of distinct parts and their consecutive recombination. Provided parallel code can perform computation more than seventeen times faster than the sequential version.
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