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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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Implementation of modular arithmetic in FPGAs and ASICs
Sýkora, Michal ; Bohrn, Marek (referee) ; Dvořák, Vojtěch (advisor)
This thesis is focused on analysis, design and implementation of modular arithmetic in FPGAs and ASICs. Its main objective is to create a C++/SystemC library, that contains synthesizable functions for operations with Montgomery reduction in modular arithmetic. Results of the implementation of Montgomery reduction are compared with results of classic algorithms for modular arithmetic.
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SystemC Memory Subsystem
Michl, Kamil ; Vaňák, Tomáš (referee) ; Hruška, Tomáš (advisor)
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
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Modelling and simulation of analog circuits in FPGA
Kotulič, Dominik ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
Bachelor thesis is focused on seeking a suitable calculation algorithm of an exponential function which could be suitably implemented in ASIC and FPGA circuits. The first part of the thesis is aimed at brief clarifying of the issue of transients in accumulation circuits and their modelling in the program PSpice. The second part deals with seeking ways of model proposals of the exponential function appropriate for the implementation in ASIC and FPGA circuits. Subsequently, in the final part of the thesis we designed and tested two calculation algorithms of the model of the exponential function that are implemented for floating point numbers.
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Design of hardware cipher module
Bayer, Tomáš ; Stančík, Peter (referee) ; Sobotka, Jiří (advisor)
This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.
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Transformation of a Processor Description in CodAL to SystemC Structures
Ondruš, Tomáš ; Hynek, Jiří (referee) ; Přikryl, Zdeněk (advisor)
The goal of this thesis is to create a generator of simulators and hardware representation of application specific processors in a SystemC language. An aim of the first part is to create a wrapper layer compatible with SystemC TLM 2.0 that wraps an existing simulator to avail modeling of transaction oriented systems. The second part is a generator of a hardware representation for the processor that is suitable not only for logical synthesis, but also for the simulation on a cycle accurate level. A final result is a state of the art solution comparable to existing generators.
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SystemC Memory Subsystem
Michl, Kamil ; Vaňák, Tomáš (referee) ; Hruška, Tomáš (advisor)
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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|
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Transformation of a Processor Description in CodAL to SystemC Structures
Ondruš, Tomáš ; Hynek, Jiří (referee) ; Přikryl, Zdeněk (advisor)
The goal of this thesis is to create a generator of simulators and hardware representation of application specific processors in a SystemC language. An aim of the first part is to create a wrapper layer compatible with SystemC TLM 2.0 that wraps an existing simulator to avail modeling of transaction oriented systems. The second part is a generator of a hardware representation for the processor that is suitable not only for logical synthesis, but also for the simulation on a cycle accurate level. A final result is a state of the art solution comparable to existing generators.
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