Original title: Implementace modulární aritmetiky do obvodů FPGA a ASIC
Translated title: Implementation of modular arithmetic in FPGAs and ASICs
Authors: Sýkora, Michal ; Bohrn, Marek (referee) ; Dvořák, Vojtěch (advisor)
Document type: Bachelor's theses
Year: 2015
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]
Táto práca sa zaoberá analýzou, návrhom a implementáciou modulárnej aritmetiky do obvodov FPGA a ASIC. Jej hlavným cieľom je vytvoriť knižnicu syntetizovateľných funkcií v jazyku C++/SystemC pre operácie v modulárnej aritmetike s využitím Montgomeryho redukcie a porovnať výsledky implementácie s klasickými algoritmami. This thesis is focused on analysis, design and implementation of modular arithmetic in FPGAs and ASICs. Its main objective is to create a C++/SystemC library, that contains synthesizable functions for operations with Montgomery reduction in modular arithmetic. Results of the implementation of Montgomery reduction are compared with results of classic algorithms for modular arithmetic.
Keywords: ASIC; FPGA; Modular arithmetic; Modular multiplication; Montgomery reduction; SystemC; ASIC; FPGA; Modulárna aritmetika; Modulárne násobenie; Montgomeryho redukcia; SystemC

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/41548

Permalink: http://www.nusl.cz/ntk/nusl-601711


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Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses