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Additional LCD Display for Laboratory Kit with a Programmable Device
Pajskr, Jaroslav ; Kubíček, Michal (referee) ; Kolouch, Jaromír (advisor)
The main part of the digital application is its user interface. Users can check the status of the programme or change its state. There are many ways to obtain a suitable interface. During the design stage the simplest interface is chosen that provides the necessary functions. In most cases the interface contains a display. This diploma thesis deals with the design of an extension board to plug in a display to a programmable device, a control algorithm for the display and the design of a simple display interface. There are two ways to design software. The first of them is achieved by the processor PicoBlaze, which contains all the required functions. The second solution is by the state machine written in VHDL language. Both solutions can be used in the same way, but the latter solution is quicker and requires less hardware resources.
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Design and Implementation of the Component for Comunication with PCI Interface
Janoušek, Michal ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This masters thesis deals with design of the component facilitating communication between PCI bus and user component. Designed component is simplifying the communication protocol between designed and user components, while advanced functions of PCI bus are preserved. Target platform is COMBO6-PTM card containing FPGA with Spartan 3 technology. Communication with PCI bus is mediated by PLX component. Thesis also contains design of simplified communication protocol.
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Acceleration of Data Encryption Algorithms in FPGA
Gajdoš, Miroslav ; Kaštil, Jan (referee) ; Šimek, Václav (advisor)
This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue.
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Partial reconfiguration methods based on programmable structures
Kolář, Jan ; Kváš, Marek (referee) ; Valach, Soběslav (advisor)
This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.
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Graphics controller for FPGA
Bartoš, Dušan ; Fujcik, Lukáš (referee) ; Pristach, Marián (advisor)
Bachelor thesis deals with a proposal of a graphic controller for FPGA circuits. Thesis describes the communication between a circuit and a monitor, RAM memory, input device (keyboard) and the manipulation with the system. Not only it includes the description of a video memory data generating program, but also it describes the communication with a monitor on the hardware level. Moreover, it suggests the possibility of controlling the video output. Finally, it discusses possible future extensions of the controller's functionality.
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Graphical interface for industrial display in gate array
Drbal, Jakub ; Macháň, Ladislav (referee) ; Pristach, Marián (advisor)
This Bachelor’s thesis deals with design and realization of graphic interface that allows rendering of characters and basic text formatting on the industrial display. This interface is designed for Spartan 3 gate array. Comunication with superior system is through serial interface. Design is separated into five parts in order to achieve easier modification of the design. The thesis also deals with design of expansion board for display connection with the development kit and design of demonstration boar for realized interfaces.
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Graphical interface for industrial display in gate array
Drbal, Jakub ; Macháň, Ladislav (referee) ; Pristach, Marián (advisor)
This Bachelor’s thesis deals with design and realization of graphic interface that allows rendering of characters and basic text formatting on the industrial display. This interface is designed for Spartan 3 gate array. Comunication with superior system is through serial interface. Design is separated into five parts in order to achieve easier modification of the design. The thesis also deals with design of expansion board for display connection with the development kit and design of demonstration boar for realized interfaces.
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Graphics controller for FPGA
Bartoš, Dušan ; Fujcik, Lukáš (referee) ; Pristach, Marián (advisor)
Bachelor thesis deals with a proposal of a graphic controller for FPGA circuits. Thesis describes the communication between a circuit and a monitor, RAM memory, input device (keyboard) and the manipulation with the system. Not only it includes the description of a video memory data generating program, but also it describes the communication with a monitor on the hardware level. Moreover, it suggests the possibility of controlling the video output. Finally, it discusses possible future extensions of the controller's functionality.
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