Original title: Grafický kontrolér pro obvody FPGA
Translated title: Graphics controller for FPGA
Authors: Bartoš, Dušan ; Fujcik, Lukáš (referee) ; Pristach, Marián (advisor)
Document type: Bachelor's theses
Year: 2011
Language: slo
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [slo] [eng]
Bakalárska práca sa zaoberá návrhom grafického kontroléru pre FPGA obvod. Popisuje spôsob komunikácie obvodu s monitorom, pamäťou RAM, zadávacím médiom (klávesnicou) a ovládanie systému. Obsahuje popis programu pre generovanie dát pre video pamäť a tiež popisuje komunikáciu s monitorom na hardvérovej úrovni. Navrhuje možnosť ovládania výstupného video signálu. Na záver diskutuje o možnostiach rozšírenia kontroléru do budúcnosti. Bachelor thesis deals with a proposal of a graphic controller for FPGA circuits. Thesis describes the communication between a circuit and a monitor, RAM memory, input device (keyboard) and the manipulation with the system. Not only it includes the description of a video memory data generating program, but also it describes the communication with a monitor on the hardware level. Moreover, it suggests the possibility of controlling the video output. Finally, it discusses possible future extensions of the controller's functionality.
Keywords: encoding.; Graphic controller; memory; program; signal generator; Spartan 3; synchronization; timing; VHDL; video signal

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/1883

Permalink: http://www.nusl.cz/ntk/nusl-240671


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses