Original title: Akcelerace šifrovacích algoritmů pomocí FPGA
Translated title: Acceleration of Data Encryption Algorithms in FPGA
Authors: Gajdoš, Miroslav ; Kaštil, Jan (referee) ; Šimek, Václav (advisor)
Document type: Bachelor's theses
Year: 2009
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Abstract: [cze] [eng]

Keywords: acceleration; DES; encryption algorithm; FITkit; FPGA; Spartan 3; VHDL; Virtex 5.; akcelerace; DES; FITkit; FPGA; Spartan 3; VHDL; Virtex 5.; šifrovací algoritmus

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/54460

Permalink: http://www.nusl.cz/ntk/nusl-571134


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses
 Record created 2024-04-02, last modified 2024-04-03


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