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Hardware Acceleration of Header Field Extraction
Polčák, Libor ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
Most network devices need to obtain specific packet header fields belonging to different network protocol headers for correct functionality. This work aims to create an efficient unit capable of application-specific packet header analysis and data extraction. The proposed unit deals with protocols used on L2, L3, and L4 layers of ISO/OSI model including tunneled protocols; it is possible to specify protocols which are to be supported. Data analysis is based on right linear grammar transformed to finite automaton. Hardware acceleration has to be exploited in order to achieve data processing of all traffic exchanged over high-speed networks. Using FPGA technology it is possible to achieve both fast and configurable data processing. The designed unit is able to process data on up to 40 Gbps networks. On-the-fly configuration of extracted header fields is supported.
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Fading channel hardware simulator
Pirochta, Pavel ; Kováč, Michal (referee) ; Maršálek, Roman (advisor)
Fading channel is a communication channel that experiences different interference and fading due to multi-path signal propagation. The fading channel is designed by the finite impulse response filter with the time-varying impulse characteristic. The realisation of this filtr is based on the TDL (Tapped Delay Line) model, which simulate signal delay and signal attenuation in each branch. The aim of this thesis is to create the VHDL design of selected fading channel simulator and its description for hardware implementation into the FPGA.
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Usage of Modern Methods for Increasing Reliability of Control System Implementations
Szurman, Karel ; Mičulka, Lukáš (referee) ; Kaštil, Jan (advisor)
At avionics control and critical systems is necessary guarantee a minimal level of fault tolerance and their high reliability. On the electronic components in these devices has an undesirable influence environment conditions and mainly cosmic ray. In this paper are described the most common failure types of semiconductor components and devices together with modern methods which can be increased the system fault tolerance and its overall reliability. There are introduced aspects of the avionic systems design due to finally certification and ways to evaluate its safety. This thesis describes design and implementation of the CAN bus control system for the FPGA platform which uses the CANAerospace application protocol. Created system design is improved by the TMR architecture. Fault tolerance of both system version is tested by the SEU framework which allows using the dynamic partial reconfiguration generate an SEU failures into running FPGA design.
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Vibration sensor
Matěj, Jan ; Pristach, Marián (referee) ; Bohrn, Marek (advisor)
This Bachelor’s thesis deals with a system for reading the radar antenna gearbox vibrations. Firstly it names different types of sensors and defines their suitability for this usage. Secondly it describes the system for data transmission from transducer to computer and also explains meaning of the measured results.
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Approximate String Matching Algorithm Implementation in FPGA
Pařenica, Martin ; Martínek, Tomáš (referee) ; Fučík, Otto (advisor)
This paper describes sequence alignment algorithms of nucleotide sequences. There are described pairwise alignment algorithms using database search or dynamic programming. Then in the paper is description of dynamic programming for multiple sequences and algorithm that builds phylogenetic trees. At the end of the first part of the paper is the description of technology FPGA. In the second part that is more practical is described implemntation of the choosen one algorithm. This part includes also examples of some multiple alignments.
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Packet Filtration in 100 Gb Networks
Kučera, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This master's thesis deals with the design and implementation of an algorithm for high-speed network packet filtering. The main goal was to provide hardware architecture, which would support large rule sets and could be used in 100 Gbps networks. The system has been designed with respect to the implementation on an FPGA card and time-space complexity trade-off. Properties of the system have been evaluated using various available rule sets. Due to the highly optimized and deep pipelined architecture it was possible to reach high working frequency (above 220 MHz) together with considerable memory reduction (on average about 72% for compared algorithms). It is also possible to efficiently store up to five thousands of filtering rules on an FPGA with only 8% of on-chip memory utilization. The architecture allows high-speed network packet filtering at wire-speed of 100 Gbps.
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Implementation of matrix decomposition and pseudoinversion on FPGA
Röszler, Pavel ; Rajmic, Pavel (referee) ; Smékal, David (advisor)
The purpose of this thesis is to implement algorithms of matrix eigendecomposition and pseudoinverse computation on a Field Programmable Gate Array (FPGA) platform. Firstly, there are described matrix decomposition methods that are broadly used in mentioned algorithms. Next section is focused on the basic theory and methods of computation eigenvalues and eigenvectors as well as matrix pseudoinverse. Several examples of implementation using Matlab are attached. The Vivado High-Level Synthesis tools and libraries were used for final implementation. After the brief introduction into the FPGA fundamentals the thesis continues with a description of implemented blocks. The results of each variant were compared in terms of timing and FPGA utilization. The selected block has been validated on the development board and its arithmetic precision was analyzed.
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Implementation of ethernet communication inteface into FPGA chip
Skibik, Petr ; Fujcik, Lukáš (referee) ; Bohrn, Marek (advisor)
The thesis deals with the implementation of Ethernet-based network communication interface into FPGA chip. VHDL programming language is used for description of the hardware. The interface includes the implementation of link-layer Ethernet protocol and network protocols such as IPv4, ARP, ICMP and UDP. The final design allows bi-directional communication on the transport-layer level of TCP/IP model. The designed interface was implemented into Virtex5 FPGA chip on development board ML506 by Xilinx.
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C++ Implementation of FPNN Structures
Pánek, Richard ; Čekan, Ondřej (referee) ; Krčma, Martin (advisor)
This master's thesis deals with the design and the C++ implementation of the Field Programmable Neural Networks (FPNNs) simulator. It briefly introduces the concept of artificial neural networks as it is the base of the FPNN concept. It presents the concept formal definitions and its calculation methods. The thesis also describes the special features of the FPNNs and the differences between the FPNNs and the classic neural networks. Furthermore, it deals with models of fault tolerant FPNNs. All the presented principles are used as the base of the developed implementation and the subsequent experiments.
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