Original title: Implementace ethernetového komunikačního rozhraní do obvodu FPGA
Translated title: Implementation of ethernet communication inteface into FPGA chip
Authors: Skibik, Petr ; Fujcik, Lukáš (referee) ; Bohrn, Marek (advisor)
Document type: Master’s theses
Year: 2011
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]

Keywords: ARP; checksum; CRC; Ethernet; FPGA.; ICMP; IEEE803.2; IP; link layer; network communication; network layer; packet; TCP/IP model; transport layer; UDP; VHDL; ARP; CRC; Ethernet; FPGA.; ICMP; IEEE803.2; IP; kontrolní součet; linková vrstva; paket; síťová komunikace; síťová vrstva; TCP/IP model; transportní vrstva; UDP; VHDL

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/1877

Permalink: http://www.nusl.cz/ntk/nusl-558631


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2024-04-02, last modified 2024-04-03


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