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Specialized Instruction Design
Koscielniak, Jan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The purpose of this thesis is to design and implement specialized instructions for RISC-V instruction set architecture. These instruction are used to accelerate a set of selected cryptographic algorithms. New instructions are implemented in Codasip Studio for 32bit processor model with RV32IM instruction set. Open source implementations were selected and edited to use new instructions. Instructions were used on respective algorithms, tested and profiled. The outcome of this thesis is instruction set extension, that enables up to seven times speed up, depending on used algorithm.
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Information System for Software Licences
Nejedlý, Jakub ; Masařík, Karel (referee) ; Burget, Radek (advisor)
This work treats the creation of an information system for software license management. The ordering company is Codasip, which deals with processor manufacturing and creation of related software tools. This company has been using its web portal and licenses management system is its expanding module. That is why the source code of the project is written, as well as the original web interface, in PHP language, using the Nette Framework. Moreover there is the LM-X technology of software licensig described here and so the deployment in a rival solution. The specifications of the product by X-Formation and Codasip's requirements are setting the basics for license system design. The design itself and the description of the implementation according to MVP design pattern, are part of this work.
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Debugging Information in Linker
Nikl, Vojtěch ; Křoustek, Jakub (referee) ; Masařík, Karel (advisor)
This thesis describes the conversion between the CCOFF object file format and the ELF file format. We start with a general object file format and its debbuging information, then we focus closely on the ELF, CCOFF and DWARF debugging information. The functionality of the CCOFF format is encapsulated in the ObjectFile class library. Then follows the description of creating an ELF object file, its filling with the proper data and its conversion back to the CCOFF format.
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Compilation of C++ Applications for Embedded Devices
Nosterský, Milan ; Přikryl, Zdeněk (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the integrations of C++ programming language and its standard C++11 into the compiler for embedded systems. This compiler is based on LLVM project and it is generated from Codasip Studio. Codasip Studio is tool for design of the aplication specific processor cores, it is also allows generate compiler, which is based on the description of semantics section in processor's instruction set for any target processor architecture. C++ is programming language based on the C, which is extended by object oriented design and many other features. C++ language allows writing of very effective code on high level of abstraction. Funcionality of implementation is tested on testsuite in last phase of master's thesis.
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Architecture Information for LLVM Compiler Optimizations
Svoboda, Jan ; Dolíhal, Luděk (referee) ; Hruška, Tomáš (advisor)
Tato práce se zabývá automatickou extrakcí informací o architektuře procesoru z jazyka CodAL. Získané informace jsou využity jako základ pro cenový model optimalizátoru překladače LLVM. V rámci práce vznikl nový systém, který vytváří cenový model, převádí jej do C++ kódu a sestavuje do dynamické knihovny. Tato knihovna je za běhu načtena překladačem a využita pro přesnější rozhodování o přínosech jednotlivých optimalizací. Výsledkem práce je průměrné 14% snížení velikosti strojového kódu programů a až 68% zlepšení výkonu generovaného kódu.
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Software Pipelining in the LLVM Compiler
Glasnák, Ondrej ; Hynek, Jiří (referee) ; Masařík, Karel (advisor)
This thesis discusses a design and implementation of the Software Pipelining, a optimization technique of loops in a program, which tries to exploit instruction-level parallelism. It is achieved by scheduling instructions in a way to overlap iterations of the loop and therefore execute them in a pipeline. This way optimization speeds up the final program. There is a detailed description of design and implementation of Swing Modulo Scheduling algorithm, an effective and efficient method for finding near-optimal plans for software-pipelined loops. This work has been done as a part of a larger project, the development of Codasip Framework. Part of this framework is the retargetable C compiler based on compiler architecture LLVM, in which this work is implemented.
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Functional Verification of Processor Execution Units
Valach, Lukáš ; Lengál, Ondřej (referee) ; Masařík, Karel (advisor)
The thesis deals with integration of functional verification into the design cycle of execution units in a hardware-software co-design environment of the Codasip system. The aim of the thesis is to design and implement a verification environment in SystemVerilog in order to verify automatically generated hardware representation of the execution units. In the introduction, advantages and basic methods of functional verification and principles of the Codasip system are discussed. Next chapters describe the process of design and implementation of the verification environment of arithmetic-logic unit as well as the analysis of the results of verification. In the end, a review of accomplished goals and the suggestions for future development of the verification environment are made.
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Modelling of M68000 Model Processor
Adamec, Ondřej ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
The goal of this bachelor's thesis is to create a model of Motorola 68000 processor using architecture description language CodAL and Codasip development environment. Architecture of the processor is presented and model structure is described. The result is a working model that has been tested to ensure its correctness.
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Modelling of 8051 Processor
Krůpa, Tomáš ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
Computer modeling is nowadays very important part of development of almost any new product. The objective of this bachelors thesis is to develop a model of 8051 microprocessor that should enlarge a portfolio of customizable processors available for Codasip platform. The complete model is described in two levels of abstraction the instruction accurate model and the cycle accurate model. For verification of the model, ANSI C programs translated by SDCC compiler were used.
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SystemC Memory Subsystem
Michl, Kamil ; Vaňák, Tomáš (referee) ; Hruška, Tomáš (advisor)
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
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