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Measurement of magnetic field stability using 40Ca+ ion
Pham, Minh Tuan ; Lešundák, Adam ; Čížek, Martin ; Podhora, L. ; Řeřucha, Šimon ; Jedlička, Petr ; Slodička, L. ; Lazar, Josef ; Číp, Ondřej
One of the main limitations in the long-term measurement of the clock transition's absolute frequency is the magnetic field's fluctuation. The time-varying fluctuation of the external magnetic field leads to frequency shifts of the Zeeman components, thereby reducing the optical clock's frequency stability over time. Currently, optical atomic references are usually implemented with the help of a single ion. However, scaling the number of ions to higher values brings an indisputable benefit in the form of a high signal-to-noise ratio and, thus to the efficiency of the entire measurement process. In this case, the ions are spread over a large area, forming so-called ionic Coulomb crystals. In addition to the spatial stability of the magnetic field, the homogeneity of the magnetic field is also significant when working with Coulomb crystals. Excessive magnetic perturbation can be greatly reduced by covering the assembly with a magnetic shield or by using permanent magnets instead of conventionally used magnetic coils. Another method is averaging over multiple-level transitions. This contribution presents a simple method for measuring the stability of the magnetic field at the ion position.
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VHDL-based implementation of CRYSTALS-Kyber components on FPGA
Jedlicka, Petr ; Hajny, Jan
CRYSTALS-Kyber is one of the finalists of the National Institute of Standards and Technology (NIST) post-quantum cryptography competition. In this paper, we deal with effective hardware-accelerated implementations of components intended for the use in the FPGA (Field Programmable Gate Array) implementation of the above-mentioned lattice-based cryptography scheme. The discussed components are NTT (Number Theoretic Transform), inverse NTT (NTT−1), CBD (Centered Binomial Distribution) and the Parse Algorithm (shortly Parse). The improved implementation of NTT (NTT−1) requires 1189 (1568) Look-Up Tables (LUTs), 1469 (2161) Flip-Flops (FFs), 28 (50) Digital Signal Processing blocks (DSPs) and 1.5 (1.5) Block Memories (BRAMs). The latency of the design is 322 (334) clock cycles at the frequency 637 MHz which makes the presented NTT (NTT−1) implementations to be currently the fastest ones. The implementations of the sampling functions (CBD and Parse) requires less than 100 LUTs and FFs with maximum latency 5 clock cycles at the frequencies over 700 Mhz. All implementations has been synthesized for the Xilinx Virtex UltraScale+ architecture.
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Web application demonstrating lattice-based cryptography
Sečkár, Martin ; Jedlička, Petr (referee) ; Ricci, Sara (advisor)
Zámer tejto práce je vyvinúť a implementovať webovú aplikáciu demonštrujúcu kryptografiu založenú na mriežkach. Aplikácia bola vyvinutá použitím programovacieho jazyku Python a kontajnerizačnej platformy Docker. Špecifickejšie, implementované moduly používajú knižnicu Bokeh a vlastnú JavaScript funkcionalitu, ktorá rozširuje danú knižnicu Bokeh. Tieto moduly sú poskytované serverom Flask, kde taktiež prebiehajú všetky výpočty pomocou knižnice numPy. Aplikácia obsahuje tri moduly popisujúce problém najbližšieho vektora, problém učenia s chybami a Boyenov kryptografický protokol založený na predchádzajúcom probléme. Užívatelia majú možnosť vizualizovať dvojdimenzionálne mriežky a prevádzať vybrané výpočty. Zdrojový kód je jednoducho rozšíriteľný a môže slúžiť ako náučná platforma. Práca taktiež obsahuje inštalačný a používateľský manuál.
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Verification of Function Blocks for FPGA
Kříž, Daniel ; Smékal, David (referee) ; Jedlička, Petr (advisor)
This master thesis is devoted to the issue of verification of function blocks for FPGA. The teoritical part of thesis describes the concept of verification, verification methodologies that provide the necessary tools for testing the design, and finally discusses the issue of Ethernet and its differences from the low-latency variant. The aim of the practical part of the master thesis is based on the acquired theoretical knowledge and selected verification methodology to build a verification environment, perform a thorough verification of the low-latency physical layer of Ethernet and finally measure the latency and throughput of this circuit.
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Postquantum Cryptography on the FPGA Platform
Dobiáš, Patrik ; Jedlička, Petr (referee) ; Malina, Lukáš (advisor)
This master thesis deals with the hardware implementations of post-quantum cryptogra- phy schemes on FPGA platforms. After the initial comparison of the candidate schemes for NIST standardization and the analysis of the previous work focusing on these schemes, Crystals-KYBER scheme was chosen and implemented. All scheme algorithms have been implemented inside a single component, minimizing resource utilization. The results of this implementation were analyzed and compared with the existing implementations. At the end of this work, the implemented scheme was deployed on Virtext UltraScale+ and tested for the use during mutually authenticated key exchange (AKE).
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Postquantum cryptography on FPGA
Győri, Adam ; Jedlička, Petr (referee) ; Smékal, David (advisor)
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation, subsequent implementation of the implementation on the FPGA process system. The work describes the issue of postquantum cryptography and VHDL programming language used to describe the functionality of hardware. Furthermore, the work deals with the functional implementation and simulation of all parts of the algorithm. Specifically, these are parts, key generation, encapsulation, and decapsulation. Algorithm implementation and simulations were performed in the Vivado software simulation environment, created by Xilinx. Subsequently, the synthesis and implementation was performed and the Intellectual property block was designed, the key part of which covered the functionality of the NEXYS A7 FPGA board was not available. The last part of the work deals with the workflow algorithm for implementation on FPGA board NEXYS A7.
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Cryptographic algorithms on FPGA
Broda, Jan ; Jedlička, Petr (referee) ; Hajný, Jan (advisor)
The master thesis is focused on developing a demonstrator which is able to transmit data not only between operating system and network FPGA card with a UltraScale+ chip but also between two network FPGA cards. The theoretical part of the master thesis describes FPGA, developing on FPGA, programming languges that are used and develoment enviroment Vivado Design Suite. The demonstrator consists of two applications developed in C language which are used for communication between operating system and the network FPGA card and two components developed in VHDL langague which are used for communication throught a network module on the network FPGA card. The demonstrator allows inserting cryptographic algorithm which would work with transmitted data. For developing on the network FPGA card was used a Network Development Kit provided by a Liberouter team from CESNET association.
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Solvency Internal models
Mertl, Jakub ; Cipra, Tomáš (advisor) ; Mazurová, Lucie (referee) ; Jedlička, Petr (referee)
Title: Solvency Internal models Author: Mgr. Ing. Jakub Mertl Abstract: The subject of thesis is assessment of calculation methods on capital adequacy of currently implemented regulation in insurance industry called Solvency II. The aim of the thesis is to build up a partial internal model fulfilling the condition of Solvency II. The thesis deals with the premium and reserve risks that are essential part of non-life business. Different approaches of risk assessment are described and aggregation of those risks as well. An important part of the thesis is a numerical example illustrating presented methods.
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