National Repository of Grey Literature 61 records found  1 - 10nextend  jump to record: Search took 0.02 seconds. 
Communication in a hardware accelerated circuit
Rosa, Michal ; Jedlička, Petr (referee) ; Smékal, David (advisor)
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks. Although one-time programmable (OTP) FPGAs are available, the dominant types are SRAM based which can be reprogrammed as the design evolves.
Communication in a hardware accelerated circuit
Rosa, Michal ; Jedlička, Petr (referee) ; Smékal, David (advisor)
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks. Although one-time programmable (OTP) FPGAs are available, the dominant types are SRAM based which can be reprogrammed as the design evolves.
Random number generation on FPGA platform
Písek, Miroslav ; Jedlička, Petr (referee) ; Dobiáš, Patrik (advisor)
The bachelor's thesis deals with the implementation of a hardware random number generator on FPGA platform. It tries to explain the basic architecture and possible FPGA configuration. In the theoretical part, the principles of random number generators are further described and then the statistical tests through which we evaluate these generators. In the following section, the existing generators designed for FPGA platforms are summarized and analyzed. A closer measurement of freely available TRNG is also underway. In the final part, there is a description of the implementation of the own random number generator. Randomness verification takes place through the NIST statistical test suite.
Smart VoIP doorbell
Čecháček, Šimon ; Jedlička, Petr (referee) ; Caha, Tomáš (advisor)
This bachelor thesis focuses on the extension of an existing VoIP communicator on a single board computer Raspberry Pi, which uses the SIP protocol. The thesis introduces, among other things, an extension for one-way video transmission and conditional relay switching. The resulting communicator is able to make a call with two-way communication, execute a defined code using DTMF codes after authorization of the called user and switch a relay. The entire device is housed in a box printed on a 3D printer. The IT security of the proposed solution has been analyzed and the code and 3D model of the chassis are available on GitHub.
Measurement of magnetic field stability using 40Ca+ ion
Pham, Minh Tuan ; Lešundák, Adam ; Čížek, Martin ; Podhora, L. ; Řeřucha, Šimon ; Jedlička, Petr ; Slodička, L. ; Lazar, Josef ; Číp, Ondřej
One of the main limitations in the long-term measurement of the clock transition's absolute frequency is the magnetic field's fluctuation. The time-varying fluctuation of the external magnetic field leads to frequency shifts of the Zeeman components, thereby reducing the optical clock's frequency stability over time. Currently, optical atomic references are usually implemented with the help of a single ion. However, scaling the number of ions to higher values brings an indisputable benefit in the form of a high signal-to-noise ratio and, thus to the efficiency of the entire measurement process. In this case, the ions are spread over a large area, forming so-called ionic Coulomb crystals. In addition to the spatial stability of the magnetic field, the homogeneity of the magnetic field is also significant when working with Coulomb crystals. Excessive magnetic perturbation can be greatly reduced by covering the assembly with a magnetic shield or by using permanent magnets instead of conventionally used magnetic coils. Another method is averaging over multiple-level transitions. This contribution presents a simple method for measuring the stability of the magnetic field at the ion position.
Compact vacuum assembly for trapping and laser cooling of 27Al+ and 40Ca+ ions
Grim, Jakub ; Vlček, Ivan ; Jedlička, Petr ; Pham, Minh Tuan ; Číp, Ondřej
We present the design of a compact vacuum chamber for trapping and laser cooling of 27Al+ a 40Ca+ ions. The vacuum chamber has been designed to a compact size to achieve good optical access to the trapped ions and ultra-high vacuum in the chamber. In combination with the Helmholtz coils, saddle coils, and magnetic shielding is achieved a homogenous magnetic field in the ion trapping area. The presented apparatus will enable quantum experiments with single ions and also Coulomb crystals.
VHDL-based implementation of CRYSTALS-Kyber components on FPGA
Jedlicka, Petr ; Hajny, Jan
CRYSTALS-Kyber is one of the finalists of the National Institute of Standards and Technology (NIST) post-quantum cryptography competition. In this paper, we deal with effective hardware-accelerated implementations of components intended for the use in the FPGA (Field Programmable Gate Array) implementation of the above-mentioned lattice-based cryptography scheme. The discussed components are NTT (Number Theoretic Transform), inverse NTT (NTT−1), CBD (Centered Binomial Distribution) and the Parse Algorithm (shortly Parse). The improved implementation of NTT (NTT−1) requires 1189 (1568) Look-Up Tables (LUTs), 1469 (2161) Flip-Flops (FFs), 28 (50) Digital Signal Processing blocks (DSPs) and 1.5 (1.5) Block Memories (BRAMs). The latency of the design is 322 (334) clock cycles at the frequency 637 MHz which makes the presented NTT (NTT−1) implementations to be currently the fastest ones. The implementations of the sampling functions (CBD and Parse) requires less than 100 LUTs and FFs with maximum latency 5 clock cycles at the frequencies over 700 Mhz. All implementations has been synthesized for the Xilinx Virtex UltraScale+ architecture.
Web application demonstrating lattice-based cryptography
Sečkár, Martin ; Jedlička, Petr (referee) ; Ricci, Sara (advisor)
Zámer tejto práce je vyvinúť a implementovať webovú aplikáciu demonštrujúcu kryptografiu založenú na mriežkach. Aplikácia bola vyvinutá použitím programovacieho jazyku Python a kontajnerizačnej platformy Docker. Špecifickejšie, implementované moduly používajú knižnicu Bokeh a vlastnú JavaScript funkcionalitu, ktorá rozširuje danú knižnicu Bokeh. Tieto moduly sú poskytované serverom Flask, kde taktiež prebiehajú všetky výpočty pomocou knižnice numPy. Aplikácia obsahuje tri moduly popisujúce problém najbližšieho vektora, problém učenia s chybami a Boyenov kryptografický protokol založený na predchádzajúcom probléme. Užívatelia majú možnosť vizualizovať dvojdimenzionálne mriežky a prevádzať vybrané výpočty. Zdrojový kód je jednoducho rozšíriteľný a môže slúžiť ako náučná platforma. Práca taktiež obsahuje inštalačný a používateľský manuál.
Verification of Function Blocks for FPGA
Kříž, Daniel ; Smékal, David (referee) ; Jedlička, Petr (advisor)
This master thesis is devoted to the issue of verification of function blocks for FPGA. The teoritical part of thesis describes the concept of verification, verification methodologies that provide the necessary tools for testing the design, and finally discusses the issue of Ethernet and its differences from the low-latency variant. The aim of the practical part of the master thesis is based on the acquired theoretical knowledge and selected verification methodology to build a verification environment, perform a thorough verification of the low-latency physical layer of Ethernet and finally measure the latency and throughput of this circuit.

National Repository of Grey Literature : 61 records found   1 - 10nextend  jump to record:
See also: similar author names
23 Jedlicka, Petr
1 Jedlička, P.
5 Jedlička, Pavel
Interested in being notified about new results for this query?
Subscribe to the RSS feed.