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Hardware Acceleration of the SUDOKU Game
Jurinek, Róbert ; Puš, Viktor (referee) ; Kaštil, Jan (advisor)
This work deals with the implementation of a hardware-based SUDOKU solver. SUDOKU terminology is described as well as SUDOKU puzzle metrics related to computer puzzle solvers. Solving techniques are introduced and possibilities of a hardware-based implementation are discussed. The implementation of the SUDOKU solver is described and the performance of the implemented unit is assessed. The designed solver was also verified on a real hardware platform. In conclusions possible unit extensions are proposed.
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Image Processing in FPGA
Maršík, Lukáš ; Španěl, Michal (referee) ; Zemčík, Pavel (advisor)
This bachelor's thesis presents a hardware realization of graphic algorithm for rendering objects described with 3D point clouds - a spatial objects representation. An FPGA (Field-Programmable Gate Array) chip coupled with a DSP (Digital Signal Processor) creates basement for implementation of function units. Is possible to decrease overall computation time by using more than one of that pair. That mean so simple distribution of load is used. The input graphical data is 3D point clouds - sets of points which are transformed into oriented circles just for purpose of rendering. Result of projection of that elements are ellipses. Such graphical representation seems to be more suitable for many purposes than the most commonly used triangle meshes. The implementation equivalent to concept is described too.
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Hardware Accelerated Functional Verification of Processor
Funiak, Martin ; Kajan, Michal (referee) ; Zachariášová, Marcela (advisor)
Functional verification belongs among the current verification approaches. Functional verification checks the correctness of the implementation of the system, due to its specification. The weakness of the functional verification approach is time consumption caused by slow software simulation of implicitly parallel hardware systems. This paper presents a solution for using a hardware accelerated functional verification of the processor. The introductory chapters form the theoretical basis for the following chapters, that include a choice of solutions, an analysis, a design of a verification environment and implementation details. The conclusion includes tests of the final product, evaluation of the results and the future work perspectives.
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Hardware-Based Acceleration of Image Filtration
Zelinka, Martin ; Slaný, Karel (referee) ; Vašíček, Zdeněk (advisor)
This bachelor's thesis deals with the hardware-based acceleration of image filtration using FIR filters. Define basic concept about digital image, describes the principle of filtration and briefly explains the techniques used to detect edges in an image and smoothing the image. The main aim of this work is the analysis of several acceleration methods of FIR filters, which are suitable for implementation in hardware, and the subsequent implementation of the selected method with the possibility of configuration changes at runtime with regard to the maximum throughput. In conclusion of this work it is described the evaluation of the method and made compared with the optimal software implementations.
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Accelerated Linear Genetic Programming in Hardware
Ťupa, Josef ; Bidlo, Michal (referee) ; Sekanina, Lukáš (advisor)
The aim of this thesis is to design and implement hardware acceleration of linear genetic programming for symbolic regression. The thesis contains a theoretical introduction into the studies of modern hardware and genetic programming design. Design and implementation of the LGP for symbolic regression is described in the rest of the thesis.
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Acceleration of Methods for Searching Palindroms and Repetitive Structures
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
Genetic information of all living organisms is stored in DNA. Exploring of its structure and function represents an important area of research in modern biology. One of the interesting structures occurring in DNA are palindromes. Based on the research they are expected to play an important role in interpreting the information stored in DNA, because they are often observed near important genes. Palindromes searching is complicated by the presence of mutations (changes in sequences of DNA elements), which increases the time complexity of algorithms. Therefore it is reasonable to study their parallelization and acceleration. The objective of this work is a study of palindromes searching methods and acceleration architecture design. The hardware unit implemented in a chip with FPGA technology placed on ml555 board can speed up the calculation up to 6 667 times in comparison with the best-known software method relying on suffix arrays.
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Algorithms for Signal Processing in FPGA
Maršík, Lukáš ; Fučík, Otto (referee) ; Zemčík, Pavel (advisor)
This master's thesis describes ways of signal processing via digital devices. Major field of interest is an analysis of Doppler radar response and then mining of informations about detected object (e.g. speed, movement direction, length, ...). There was realized too little research, that's why borrowing some procedures from different branches not too much related to the IT is necessary. In case of using very complex methods that are easy to parallel, hardware implementation on the FPGA is supposed. With transceiver there is created a very powerful on-line system able to process most of tasks real-time. Then processed and transformed data are sent to the output so visualization and display can be made.
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Hardware Accelerated Functional Verification
Zachariášová, Marcela ; Kotásek, Zdeněk (referee) ; Kajan, Michal (advisor)
Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.
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Acceleration of Network Traffic Encryption
Koranda, Karel ; Kajan, Michal (referee) ; Polčák, Libor (advisor)
This thesis deals with the design of hardware unit used for acceleration of the process of securing network traffic within Lawful Interception System developed as a part of Sec6Net project. First aim of the thesis is the analysis of available security mechanisms commonly used for securing network traffic. Based on this analysis, SSH protocol is chosen as the most suitable mechanism for the target system. Next, the thesis aims at introduction of possible variations of acceleration unit for SSH protocol. In addition, the thesis presents a detailed design description and implementation of the unit variation based on AES-GCM algorithm, which provides confidentiality, integrity and authentication of transmitted data. The implemented acceleration unit reaches maximum throughput of 2,4 Gbps.
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Accelerated Graphical User Interfaces
Navrátil, Ladislav ; Maršík, Lukáš (referee) ; Beran, Vítězslav (advisor)
Tato práce je zaměřena na multiplatformní grafická uživatelské rozhraní a jejich hardwarovou akceleraci. Popisuje, co to uživatelské rozhraní jsou a srovnává nástroje na jejich tvorbu a způsoby jejich realizace. Hlavním bodem je vlastní návrh a implementace nástroje na tvorbu multiplatformních hardwarově akcelerovaných grafických uživatelských rozhraní. Srovnává vlastní koncept s existujícími řešeními, a uvádí ho do praxe na projektu s externí firmou.
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