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Application Specific Processor for Stateful Network Traffic Processing
Kučera, Jan ; Matoušek, Jiří (referee) ; Kekely, Lukáš (advisor)
This bachelor's thesis deals with the design and implementation of an application-specific processor for high-speed network traffic processing. The main goal is to provide complex system for hardware acceleration of various network security and monitoring applications. The application-specific processor (hardware part of the system) is implemented on an FPGA card and has been designed with respect to be used in 100 Gbps networks. The design is based on the unique combination of high-speed hardware processing and flexible software control using a new concept called Software Defined Monitoring (SDM). The performance and throughput of the proposed system has been verified and measured.
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IP core for BLDC motor control
Hráček, Marek ; Bohrn, Marek (referee) ; Dvořák, Vojtěch (advisor)
This diploma thesis is about using vector control (or field-oriented control) of synchronous BLDC and PMSM motors on FPGAs. First part describes basic theory of these motors and how to control them. Then vector control is detailed and its parts as (or Clarke) and Park transformation. Rest of the thesis deals with the design of universal controller with adjustable accuracy in VHDL language. Data is separated from computing part which utilizes custom arithmetic-logic unit. In the last part of the thesis the design is tested in simulator using model of PMSM motor.
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Implementation of 400 Gb/s Ethernet PCS layer to FPGA
Kolařík, Jaroslav ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This master thesis deals with the design of the 400GBASE-R PCS in accordance with the IEEE 802.3bs-2017 standard which defines 400 Gbps Ethernet. The first part of this thesis focuses on general architecture of FPGA and its possible variants for implementation for 400 Gbps Ethernet communication, therefore there is description of those architectures and its resources. The next part describes progression of the Ethernet and its connection to the ISO/OSI reference model. The next section of this thesis is about description of physical layer of Ethernet for 400 Gbps version, after which follows design of PCS unit and its implementation with use of resources of selected FPGA. In the last part of this thesis is description of the simulation of the implemented unit. Achieved results and outcomes of this master thesis are evaluated in a conclusion.
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Serial communication peripheries development in FPGA
Štraus, Pavel ; Adamec, Filip (referee) ; Frýza, Tomáš (advisor)
This bachelor’s thesis is about two peripheries. First periphery creates from input parallel signals one output serial signal. This serial signal contains a start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count is set with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. Of course we have choice between even parity bit or odd parity bit. After parity bit there is one stop bit or there are two stop bits. Second periphery realizes I2C bus. This communication is between two devices. First device is called master and creates the communication with second device called slave. For communication there are two bidirectional lines. The first line is called SDA, which is a serial data line and second line is a serial clock line called SCL. Communication begins with a start condition. That means line SDA go from high to low while SCL is high and communication is terminate with a stop condition. That means line SDA go from low to high while SCL is high. The peripheries are programming in VHDL language and implemented in FPGA device. After successful simulation in free software ISE WebPACK the peripheries was realized in the development board V2MB1000 with device XC2V1000.
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Microprocessor system IP core generator
Kerber, Rostislav ; Tošovský, Petr (referee) ; Kubíček, Michal (advisor)
This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.
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Audio synthesizer in FPGA chip
Tomko, Jakub ; Pristach, Marián (referee) ; Bohrn, Marek (advisor)
This thesis analyses methods of sound synthesis. Advantages and disadvantages of application of individual methods in music synthetizers are evaluated. Based on piano sound analysis, the suitable method for synthesizer's design is chosen. Synthesizer has been implemented in FPGA of Spartan-3 Development Board.
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Advanced Editor of VHDL Files
Kliment, Vojtěch ; Košař, Vlastimil (referee) ; Novotňák, Jiří (advisor)
This bachelor's thesis deals with an evolution of an application, with which the designer of digital systems can insert and connect components of VHDL entity easier. You can find an introduction to the VHDL language here and the ways how to design digital systems with VHDL. The reasons of using synthesizable templates will be described. Next part is a description of a design and an implementation of an editor, which makes it easy to design by an graphic interface.
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Laboratory kit for design work with Altera CPLD devices
Gajdošík, Petr ; obrany, Petr Bojda, Univerzita (referee) ; Kolouch, Jaromír (advisor)
In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The product is used for development and demonstration of applications in CPLD devices made by Altera company. The kit is designed for Altera programming cables and Presto (made by ASIX). Input signals are implemented by a set of switches and buttons on the board. Output states are displayed by LED diods, possibly connected to multiplex the display. The user can connect to external devices via external inputs. Thesis is also aimed at the design PCB of the laboratory kit, subsequent production, recovery and verification of compatibility ALTERA and PRESTO programmers. End of the thesis aims on working with the Quartus II design environment. In particular, it is a guide to working with templates and simulation of VHDL designs.
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Image Processing in FPGA
Přibyl, Bronislav ; Seeman, Michal (referee) ; Zemčík, Pavel (advisor)
Images for scientific purposes are taken by optical devices, such as microscopes, cameras etc., which usually consist of system of lenses and optical sensor. Most lenses suffer from various distortions. Geometrical distortion may not be acceptable for example for precise distance measurement in the image. This thesis describes fast algorithm for separable image resampling capable of correcting smooth geometrical distortions caused by lenses. An FPGA implementation of this algorithm is also described.
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