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Framework for Dynamic Partial Reconfiguration of Virtex-5 FPGA
Raček, Jakub ; Viktorin, Jan (referee) ; Matoušek, Jiří (advisor)
The thesis is focused on design and implementiation of a framework for Dynamic Partial Reconfiguration for FPGA architecture Virtex-5. The aim of the framework is to simplify creating applications with hardware accelerators using Dynamic Partial Reconfiguration. Using this framework, a demonstration application was created for pattern-matching incoming network packets. The process of Dynamic Partial Reconfiguration is controlled by GNU/Linux type operating system, which runs on MicroBlaze processor. This also allows to run less demanding applications and the processing of packets using software.
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Acceleration of Data Encryption Algorithms in FPGA
Gajdoš, Miroslav ; Kaštil, Jan (referee) ; Šimek, Václav (advisor)
This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue.
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Acceleration of Transistor-Level Evolutionary Design of Digital Circuits Using Zynq
Mrázek, Vojtěch ; Sekanina, Lukáš (referee) ; Vašíček, Zdeněk (advisor)
The goal of this project is to design a hardware unit that is designed to accelerate evolutionary design of digital circuits on transistor level. The project is divided to two parts. The first one describes design methods of the MOSFET circuits and issues of evolutionary algorithms. It also analyses current results in this domain and provides a new method for the design and optimization. The second part describes proposed unit that accelerates the new method on the circuit Zynq which integrates ARM processor and programmable logic. The new method functionality has been empirically analysed in the task of optimization of few circuits with more inputs. The hardware unit has been tested for designing of gates on transistor level.
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Accelaration of RSA on GPUs
Balogh, Tomáš ; Jaroš, Jiří (referee) ; Vašíček, Zdeněk (advisor)
This bachelor's thesis discusses implementation of RSA algorithm using Montgomery multiplication for graphic cards. There are four versions of implementation created for CUDA platform with aim to achieve as high computation acceleration as possible compared to processor computation. Acceleration of computation is among other things achieved by parallelization of arithmetic operations addition and multiplication of large numbers.
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Acceleration of Object Detection Using Classifiers
Juránek, Roman ; Kälviäinen, Heikki (referee) ; Sojka, Eduard (referee) ; Zemčík, Pavel (advisor)
Detekce objektů v počítačovém vidění je složítá úloha. Velmi populární a rozšířená metoda pro detekci je využití statistických klasifikátorů a skenovacích oken. Pro učení kalsifikátorů se často používá algoritmus AdaBoost (nebo jeho modifikace), protože dosahuje vysoké úspěšnosti detekce, nízkého počtu chybných detekcí a je vhodný pro detekci v reálném čase. Implementaci detekce objektů je možné provést různými způsoby a lze využít vlastnosti konkrétní architektury, pro urychlení detekce. Pro akceleraci je možné využít grafické procesory, vícejádrové architektury, SIMD instrukce, nebo programovatelný hardware. Tato práce představuje metodu optimalizace, která vylepšuje výkon detekce objektů s ohledem na cenovou funkci zadanou uživatelem. Metoda rozděluje předem natrénovaný klasifikátor do několika různých implementací, tak aby celková cena klasifikace byla minimalizována. Metoda je verifikována na základním experimentu, kdy je klasifikátor rozdělen do předzpracovací jednotku v FPGA a do jednotky ve standardním PC.
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Echo state neural network for stock market prediction
Pospíchal, Ondřej ; Mašek, Jan (referee) ; Burget, Radim (advisor)
This thesis deals with an echo state network and with acceleration of its learning by implementing the echo state network on a graphics processor. The theoretical part consists of the description of neural networks and some selected types of neural networks, on which is based the echo state network. After that, there are some other algorithms described used for time series analysis and last but not least, the tools that were used in the practical part of the thesis were briefly described. The practical part describes the creation of the accelerated version of the echo state network. After that, there is described the creation of input data sets of real financial indexes, on which the echo state network and the other algorithmns were then tested. By analyzing this accelerated version it was found that its learning speed did not reach the theoretical expectations. The accelerated version works slower, but with greater precision. By analyzing the results of the measurement of the other algorithmns it was found that the highest precision is achieved by solutions based on the neural network principle.
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Acceleration of Burrows-Wheeler Transform Using GPU
Zahradníček, Tomáš ; Drábek, Vladimír (referee) ; Šimek, Václav (advisor)
This thesis deals with Burrows-Wheeler transform (BWT) and possibilities of acceleration of this transform on graphics processing unit (GPU). Methods of compression based on BWT are introduced, as well as software libraries CUDA and OpenCL for writing programs for GPU. Parallel variants of BWT are implemented, as well as following steps necessary for compression, using CUDA library. Amount of compression of used approaches are tested and parallel versions are compared to their sequential counterparts.
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Acceleration of Algorithms for Approximate String Matching
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The objective of this bachelor's thesis is to design and implement architecture for FPGA chips that accelerates matching of two strings and scoring them for similarity. Used processes come from bioinformatics algorithms, especially Needleman-Wunsch and Smith-Waterman. Due to general design and generic implementation in VHDL the unit is able to compare any sequences of characters, which is a task widely used in many branches of informatics from database searches (where approximate matching allows discovery of spelling errors) to spam detection. Depending on task specification the acceleration speed up against common software solution can reach orders of hundreds or even thousands.
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Acceleration of 3D Image Processing Using GPU
Jochlík, Jakub ; Klepárník, Petr (referee) ; Španěl, Michal (advisor)
This thesis proposes a solution for acceleration of large 3D image data filtering by using the compute power of graphic cards. This solution uses OpenCL platform to dedicate all necessary computation onto graphical core of the graphic card and furthermore optimize this process using on-board local memory. Design and implementation of the mentioned approach is mainly focused on Sobel Operator.
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Evolutionary Design of Collective Communications Accelerated by GPUs
Tyrala, Radek ; Dvořák, Václav (referee) ; Jaroš, Jiří (advisor)
This thesis provides an analysis of the application for evolutionary scheduling of collective communications. It proposes possible ways to accelerate the application using general purpose computing on graphics processing units (GPU). This work offers a theoretical overview of systems on a chip, collective communications scheduling and more detailed description of evolutionary algorithms. Further, the work provides a description of the GPU architecture and its memory hierarchy using the OpenCL memory model. Based on the profiling, the work defines a concept for parallel execution of the fitness function. Furthermore, an estimation of the possible level of acceleration is presented. The process of implementation is described with a closer insight into the optimization process. Another important point consists in comparison of the original CPU-based solution and the massively parallel GPU version. As the final point, the thesis proposes distribution of the computation among different devices supported by OpenCL standard. In the conclusion are discussed further advantages, constraints and possibilities of acceleration using distribution on heterogenous computing systems.
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