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A Generator of Arithmetic Circuits
Klhůfek, Jan ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor)
The aim of this bachelor thesis is to present the design and implementation of an arithmetic circuit generator. The generator focuses on generating various output representations of arithmetic circuits in flattened and hierarchical forms using the Python programming language. The work first deals with the specification of HW structures of individual arithmetic circuits and the corresponding ways of describing these structures into various representations. Followed by an introduction to the concept and details of the implementation of a tool called ArithsGen, which is able to generate arithmetic circuits and export them to various output representations. The output representations are then used for fast and simple simulation of the designed circuits (C), to describe the hardware structures and perform logic synthesis (Verilog), to formal verify the designs (BLIF) or to globally optimize the circuits using the evolutionary strategy (CGP). Finally, the generated representations were individually tested and compared with each other using the results obtained from logic synthesis.
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The Strengths and Limitations of Input-Output Analysis in Evaluating Fiscal Policy
Líšková, Lenka ; Baxa, Jaromír (advisor) ; Kukačka, Jiří (referee)
"The Strengths and Limitations of Input-Output Analysis in Evaluating Fiscal Policy" by Bc. Lenka Liskova Abstract: The thesis addresses the recent debates on suitable macroeconomic policy and calls for an alternative evaluation and forecasting method of economic impact, by assessing the applicability of Leontief's input- output model. We concentrate on providing an insight into the entire process of input-output analysis, which yields computation of simple input-output multipliers - output, gross value added and income multi- pliers. Thanks to the ability to capture linkages in the economy, com- puted multipliers are used as a tool to evaluate the effects of vehicle scrappage schemes and ICT infrastructure investment subsidies applied within a sample of diverse developed countries - Australia, Germany, Japan, UK and USA. We also aim to provide a sufficient explanation of the input-output model and a computation manual based on the example of the Leontief open model and calculation of simple multipli- ers. In our research, we numerically evaluate the effects of fiscal stim- ulus measures in the automobile industry and ICT sector and provide their comparison among 5 countries with different industry structures. Most importantly, the thesis provides a suggestion for policy makers to consider applying input-output...
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Processor Overclocking
Horký, Jan ; Adámek, Martin (referee) ; Novotný, Radovan (advisor)
The aim of bachelor's thesis was to describe and explain processor overclocking and its use. Suitable processor was chosen and its operational frequency was increased by increasing value of multiplier and changing frequency of FSB. Multiplier and frequency of FSB were increased by the smallest step, which motherboard allowed, to value when computer was unstable. Processor was tested by stress and performance tests for each frequency. Change of power consumption was also measured. At the end, both methods were compared.
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Adjoint Differential Equations
Kmenta, Karel ; Pindryč, Milan (referee) ; Kunovský, Jiří (advisor)
This project deals with solving differential equations. The aim is find the correct algorithm transforming differential equations of higher order with time variable coefficients to equivalent systems of differential equations of first order. Subsequently verify its functionality for equations containing the involutioin goniometrical functions and finally implement this algorithm. The reason for this transformation is requirement to solve these differential equations by programme TKSL (Taylor Kunovský simulation language).
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Crossover in Cartesian Genetic Programming
Vácha, Petr ; Vašíček, Zdeněk (referee) ; Sekanina, Lukáš (advisor)
Optimization of digital circuits still attracts much attention not only of researchers but mainly chip producers. One of new the methods for the optimization of digital circuits is cartesian genetic programming. This Master's thesis describes a new crossover operator and its implementation for cartesian genetic programming. Experimental evaluation was performed in the task of three-bit multiplier and five-bit parity circuit design.
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Arithmetic Circuit Generator
Bolješik, Michal ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
The goal of this thesis is to design and implement a tool that would be able to generate a description of various types of arithmetic circuits, such as adders and multipliers, that are involved in more complex systems (filters, transformations, etc.). The first part of the thesis deals with analysis of different types of adders and multipliers on either theoretical or practical level. In the second part there is a description of the design and implementation of the tool created in Python language. On base of parameters, the tool is able to generate hierarchical or flattened description of various circuits in formats aimed for visualization, simulation and validation. In the end, the tool is used to compare different designs of adders and multipliers.
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Digital Programmable Building Blocks with the Residue Number Representation
Sharoun, Assaid Othman ; Mikula, Vladimír (referee) ; Šimčák, Marek (referee) ; Musil, Vladislav (advisor)
V systému s kódy zbytkových tříd je základem skupina navzájem nezávislých bází. Číslo ve formátu integer je reprezentováno kratšími čísly integer, které získáme jako zbytky všech bází, a aritmetické operace probíhají samostatně na každé bázi. Při aritmetických operacích nedochází k přenosu do vyšších řádů při sčítání, odečítání a násobení, které obvykle potřebují více strojového času. Srovnávání, dělení a operace se zlomky jsou komplikované a chybí efektivní algoritmy. Kódy zbytkových tříd se proto nepoužívají k numerickým výpočtům, ale jsou velmi užitečné pro digitální zpracování signálu. Disertační práce se týká návrhu, simulace a mikropočítačové implementace funkčních bloků pro digitální zpracování signálu. Funkční bloky, které byly studovány jsou nově navržené konvertory z binarní do reziduální reprezentace a naopak, reziduální sčítačka a násobička. Nově byly také navržené obslužné algoritmy.
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Servodrive Clamping Unit
Štefánek, Tomáš ; Plšek,, Ladislav (referee) ; Foller, Bronislav (advisor)
The aim of this thesis is to design a clamping unit with mechanical multiplier. Unit will serve as a technological clamping element in the technical equipment. My task was to select the method of construction and design driving main unit for grip jaw. I chose a solution with a mechanical multiplier. The frame unit is made up of fixed and sliding clamping jaw and is self. Unit is designed as a built module. The entire structure must be designed to meet the initial parameters specified in the award of thesis. The main parameters include clamping strength of 80kN, the extent of working stroke 15 mm and the size of a scroll, which is 250 mm. They are also listed in the award size constraints: the length, width, height dimensions and the coupling unit.
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Charge Pumps
Hála, Jaroslav ; Bajer, Arnošt (referee) ; Horák, Michal (advisor)
This work deals with issues of correct choose and simulations of voltage multipliers and charge pumps used in electronics. Work contents enumeration of many types of circuits and their propriety for various usage with cost minimisation.
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UHF band front-end of quadrature receiver
Tiller, Jakub ; Špaček, Jiří (referee) ; Kasal, Miroslav (advisor)
The object of this master's thessis is study and description of RF circuits, which are used for receiveing. This work is also aimed to design this circuits and their simulation in Ansoft Designer software. Focus is placed to the standard parameters of receiving technology. The description of amplifier design is presented in this work. Parameters of this amplifier are optimalized to low noise figure. Frequency multiplier designs are included in this project.
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