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Cyclic acceleration method for electrical machines measurement
Ředina, Ondřej ; Ctibor, Jiří (referee) ; Červinka, Dalibor (advisor)
The bachelor thesis deals with the cyclic acceleration method of measuring and loading electrical machines. The thesis contains a description of the measuring method and processing of measured data. The application of the method was realized in the company AVL Moravia s. r. o. The processing of the measured data in the form of a sine wave was performed in the MATLAB program. At the end of the thesis are summarized the inaccuracies of measurements and following optimization of this method.
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Analysis of Selected Manoeuvres of Bicyclists
Doseděl, Jan ; Ptáček, Petr (referee) ; Semela, Marek (advisor)
Master thesis titled “Analysis of selected manoeuvres of bicyclists” in the first part deals with the history of bicycles, construction, division of bicycles and introduces–traffic accidents of cyclists and national legislation. Practical measurements with bicyclists is in the second part of this thesis. Cyclists performed deceleration on three surfaces, acceleration and a manoeuver, in which cyclist looked behind himself before changing the direction. The evaluation of all measurements and comparison with other similar works has been made in the last chapters.
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Compiler for EdkDSP Platform
Baručák, Robert ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Goal of this bachelor's thesis was to create a compiler system for EdkDSP platform. Two different approaches to construction of compiler system for multiprocessor platform are presented. Compiler is based on LLVM compiler infrastructure. As a result, two versions of compiler system utilising hardware capabilities of EdkDSP were created. Developed solutions have a few constraints which are discussed in this paper.
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Analysis of Selected Manoeuvres of Bicyclists
Špačková, Kateřina ; Belák, Michal (referee) ; Semela, Marek (advisor)
This diploma thesis Analysis of selected manoeuvres of bicyclists deals with the history and development of the bicycles, further their division of, construction, analysis accident and national legislation in the theoretical part. The practical part of the master thesis is devoted to the measurements of the bicycles. Specifically, it is about acceleration, deceleration, transverse movement, ride in the curve and looking back before changing the direction. For measuring are selected different type of bikes with different construction. The results of individual measurements are evaluated in the end of the diploma thesis.
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Acceleration of Symbolic Regression Using Cartesian Genetic Programming
Hodaň, David ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
This thesis is focused on finding procedures that would accelerate symbolic regressions in Cartesian Genetic Programming. It describes Cartesian Genetic Programming and its use in the task of symbolic regression. It deals with the SIMD architecture and the SSE and AVX instruction set. Several optimizations that lead to a significant acceleration of evolution in Cartesian Genetic Programming are presented. A method of a bit-level parallel simulation that uses AVX2 vectors allows to process 256 input combinations of a logic circuit in paralell. Similarly it is possible to use a byte-level parallel simulation and work with 32 bytes when evolving an image filter. A new method of batch mutation can accelerate the evolution of combinational logic circuits thousand times depending on the problem size. For example, using a combination of these and other methods the evolution of 5 x 5b multipliers took 5.8 seconds on average on an Intel Core i5-4590 processor.
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Framework for Dynamic Partial Reconfiguration of Virtex-5 FPGA
Raček, Jakub ; Viktorin, Jan (referee) ; Matoušek, Jiří (advisor)
The thesis is focused on design and implementiation of a framework for Dynamic Partial Reconfiguration for FPGA architecture Virtex-5. The aim of the framework is to simplify creating applications with hardware accelerators using Dynamic Partial Reconfiguration. Using this framework, a demonstration application was created for pattern-matching incoming network packets. The process of Dynamic Partial Reconfiguration is controlled by GNU/Linux type operating system, which runs on MicroBlaze processor. This also allows to run less demanding applications and the processing of packets using software.
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Acceleration of Data Encryption Algorithms in FPGA
Gajdoš, Miroslav ; Kaštil, Jan (referee) ; Šimek, Václav (advisor)
This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue.
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Acceleration of Transistor-Level Evolutionary Design of Digital Circuits Using Zynq
Mrázek, Vojtěch ; Sekanina, Lukáš (referee) ; Vašíček, Zdeněk (advisor)
The goal of this project is to design a hardware unit that is designed to accelerate evolutionary design of digital circuits on transistor level. The project is divided to two parts. The first one describes design methods of the MOSFET circuits and issues of evolutionary algorithms. It also analyses current results in this domain and provides a new method for the design and optimization. The second part describes proposed unit that accelerates the new method on the circuit Zynq which integrates ARM processor and programmable logic. The new method functionality has been empirically analysed in the task of optimization of few circuits with more inputs. The hardware unit has been tested for designing of gates on transistor level.
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Accelaration of RSA on GPUs
Balogh, Tomáš ; Jaroš, Jiří (referee) ; Vašíček, Zdeněk (advisor)
This bachelor's thesis discusses implementation of RSA algorithm using Montgomery multiplication for graphic cards. There are four versions of implementation created for CUDA platform with aim to achieve as high computation acceleration as possible compared to processor computation. Acceleration of computation is among other things achieved by parallelization of arithmetic operations addition and multiplication of large numbers.
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