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Processing units of last generation processors and their utilization
Šlenker, Samuel ; Pavlíček, Tomáš (referee) ; Balík, Miroslav (advisor)
The aim of this thesis was to study and subsequently process the differences between the older instruction sets and newer instruction sets, to specify the benefits of the individual extensions, to compare the way of computations of the individual SIMD processing units and to compare the implementation of these processing units in Intel and AMD companies. Part of this work are two theoretical introductions to laboratory tasks.
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Acceleration of Object Detection Using Classifiers
Juránek, Roman ; Kälviäinen, Heikki (referee) ; Sojka, Eduard (referee) ; Zemčík, Pavel (advisor)
Detekce objektů v počítačovém vidění je složítá úloha. Velmi populární a rozšířená metoda pro detekci je využití statistických klasifikátorů a skenovacích oken. Pro učení kalsifikátorů se často používá algoritmus AdaBoost (nebo jeho modifikace), protože dosahuje vysoké úspěšnosti detekce, nízkého počtu chybných detekcí a je vhodný pro detekci v reálném čase. Implementaci detekce objektů je možné provést různými způsoby a lze využít vlastnosti konkrétní architektury, pro urychlení detekce. Pro akceleraci je možné využít grafické procesory, vícejádrové architektury, SIMD instrukce, nebo programovatelný hardware. Tato práce představuje metodu optimalizace, která vylepšuje výkon detekce objektů s ohledem na cenovou funkci zadanou uživatelem. Metoda rozděluje předem natrénovaný klasifikátor do několika různých implementací, tak aby celková cena klasifikace byla minimalizována. Metoda je verifikována na základním experimentu, kdy je klasifikátor rozdělen do předzpracovací jednotku v FPGA a do jednotky ve standardním PC.
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Algorithm Acceleration on Larrabee Platform
Veselý, Ivo ; Seeman, Michal (referee) ; Zemčík, Pavel (advisor)
Intel Larrabee is one of the first of fully programmable graphical architectures. Thesis describes this many-core architecture by hardware implementation and programmer's model point of view. Larrabee bets on many complete in-order cores, built over x86 instruction set. Cores contains four hardware threads, each with it's own register file, and new vector processing unit. Vector processing unit together with instruction set extension rapidly increases system performance. New cache modes helps to increase throughput even when irregular data structures. This architecture is not focused only on computer graphics nor image processing, but all parallel tasks. Second part of this text deals with hologram synthesis. Specifically, it brings two new methods for patch of point light sources generation with concrete radiation.
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Search of Corresponding Objects in a Pair of Images
Vrbenský, Andrej ; Herman, David (referee) ; Orság, Filip (advisor)
This thesis is aimed on area of stereoscopy. At first, there is some space dedicated to stereoscopic theory, primarily to seaching of corresponding objects in a stereo image pair. Main attention is given to template matching methods, which are based on intesity comparison. Then we try to optimize these methods with SIMD SSE instructions and run some tests with image examples. These methods are implemented in C++ and also in assembly language.
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Ray-tracing Using IPP Library
Kukla, Michal ; Havel, Jiří (referee) ; Hradiš, Michal (advisor)
Master thesis is dealing with design and implementation of ray-tracing and path-tracing using IPP library. Theoretical part discusses current trends in acceleration of selected algorithms and also possibilities of parallelization. Design of ray-tracing and path-tracing algorithm and form of parallelization are described in proposal. This part also discusses implementation of adaptive sampling and importance sampling with Monte Carlo method to accelerate path-tracing algorithm. Next part is dealing with particular steps in implementation of selected rendering methods regarding IPP library. Implementation of network interface using Boost library is also discussed. At the end, implemented methods are subjected to performance and quality test. Final product of this thesis is server aplication capable of handling multiple connections which provides visualisation and client application which implements ray-tracing and path-tracing.
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Algortihm Optimization Using SIMD Instructions
Sedláček, Marek ; Rydlo, Štěpán (referee) ; Orság, Filip (advisor)
This thesis talks about techniques which can be used to optimize run time of algorithms. For a demonstration of these techniques algorithms from different fields were chosen, namely particle swarm optimization, circle drawing algorithm and image (matrix) rotation algorithm. These algorithms were written in Python 3, C language and assembly language using SIMD instructions. While writing these codes emphases was placed on code efficiency. These practices were in this thesis described and compared, same as the impact on algorithm optimization. Performed tests upheld expected potential of SIMD technology for optimization, but also that this approach cannot be used in all cases. In case of circle drawing the SIMD approach achieved more than ten times better speeds than the serial implementation in C and more than one thousand times better speed than Python 3 implementation. In case of particle swarm optimization the result was opposite -- serial C implementation achieved a better speed than SIMD implementation.
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Acceleration of Vector and Cryptographic Operations on x86-64 Platform
Šlenker, Samuel ; Martinásek, Zdeněk (referee) ; Balík, Miroslav (advisor)
The aim of this thesis was to study and subsequently process a comparison of older and newer SIMD processing units of modern microprocessors on the x86-64 platform. The thesis provides an overview of the fastest computations of vector operations with matrices and vectors, including corresponding source codes. Furthermore, the thesis is focused on authenticated encryption, specifically on block cipher AES operating in Galois Counter Mode, and on a discussion of possibilities of instruction sets for cryptographic support.
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Optimization of a Processor Core for the OpenCV Library
Benna, Filip ; Hynek, Jiří (referee) ; Hruška, Tomáš (advisor)
This bachelor's thesis deals with compilation of OpenCV library with Codix RISC processor core as the target machine and following optimization of chosen applications based on this library. Process of optimization is based on extensibility of the processor core, therefore this thesis theoretically describes and also shows on example extending the processor's instruction set with vector instructions. The thesis also contains the results of the optimization and their comparison with the not optimized application.
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Lifting Scheme Cores for Wavelet Transform
Bařina, David ; Kälviäinen, Heikki (referee) ; Sojka, Eduard (referee) ; Zemčík, Pavel (advisor)
Práce se zaměřuje na efektivní výpočet dvourozměrné diskrétní vlnkové transformace. Současné metody jsou v práci rozšířeny v několika směrech a to tak, aby spočetly tuto transformaci v jediném průchodu, a to případně víceúrovňově, použitím kompaktního jádra. Tohle jádro dále může být vhodně přeorganizováno za účelem minimalizace užití některých prostředků. Představený přístup krásně zapadá do běžně používaných rozšíření SIMD, využívá hierarchii cache pamětí moderních procesorů a je vhodný k paralelnímu výpočtu. Prezentovaný přístup je nakonec začleněn do kompresního řetězce formátu JPEG 2000, ve kterém se ukázal být zásadně rychlejší než široce používané implementace.
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