|
|
High Order Modulation Digital Modulator
Žižka, Josef ; Hubík,, Vladimír (referee) ; Šebesta, Jiří (advisor)
The object of this work is to meet readers with the basic principle and solution of high order digital modulator with integrated circuit AD9957 produced by the company Analog Devices. Block diagram and final scheme of the modulator and device construction is presented. Standard USB interface for communication, control and data transmission between modulator and host represented by personal computer is applied. The project describes following parts of the designed system: PCB layout, control firmware of MCU and application program running under PC. In the conclusion, chosen results of measurement are described and evaluated.
|
|
|
Hardware Acceleration of Analysis and Header Field Extraction
Polčák, Libor ; Tobola, Jiří (referee) ; Kořenek, Jan (advisor)
This work deals with packet analysis and processing for high speed networks using FPGA. Model of the analysis and hardware architecture have been proposed. Protocols can be specified in XML. Automated tool is able to convert this specification to VHDL. As mul- tiple bytes and protocol headers are processed within one clock cycle simultaneously, the proposed unit is able to handle packet processing on 10 Gbps speed and higher.
|
|
|
Acceleration of Methods for Searching Palindroms and Repetitive Structures
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
Genetic information of all living organisms is stored in DNA. Exploring of its structure and function represents an important area of research in modern biology. One of the interesting structures occurring in DNA are palindromes. Based on the research they are expected to play an important role in interpreting the information stored in DNA, because they are often observed near important genes. Palindromes searching is complicated by the presence of mutations (changes in sequences of DNA elements), which increases the time complexity of algorithms. Therefore it is reasonable to study their parallelization and acceleration. The objective of this work is a study of palindromes searching methods and acceleration architecture design. The hardware unit implemented in a chip with FPGA technology placed on ml555 board can speed up the calculation up to 6 667 times in comparison with the best-known software method relying on suffix arrays.
|
|
|
Implementation of matrix decomposition and pseudoinversion on FPGA
Röszler, Pavel ; Rajmic, Pavel (referee) ; Smékal, David (advisor)
The purpose of this thesis is to implement algorithms of matrix eigendecomposition and pseudoinverse computation on a Field Programmable Gate Array (FPGA) platform. Firstly, there are described matrix decomposition methods that are broadly used in mentioned algorithms. Next section is focused on the basic theory and methods of computation eigenvalues and eigenvectors as well as matrix pseudoinverse. Several examples of implementation using Matlab are attached. The Vivado High-Level Synthesis tools and libraries were used for final implementation. After the brief introduction into the FPGA fundamentals the thesis continues with a description of implemented blocks. The results of each variant were compared in terms of timing and FPGA utilization. The selected block has been validated on the development board and its arithmetic precision was analyzed.
|
|
|
Packet Filtration in 100 Gb Networks
Kučera, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This master's thesis deals with the design and implementation of an algorithm for high-speed network packet filtering. The main goal was to provide hardware architecture, which would support large rule sets and could be used in 100 Gbps networks. The system has been designed with respect to the implementation on an FPGA card and time-space complexity trade-off. Properties of the system have been evaluated using various available rule sets. Due to the highly optimized and deep pipelined architecture it was possible to reach high working frequency (above 220 MHz) together with considerable memory reduction (on average about 72% for compared algorithms). It is also possible to efficiently store up to five thousands of filtering rules on an FPGA with only 8% of on-chip memory utilization. The architecture allows high-speed network packet filtering at wire-speed of 100 Gbps.
|
|
|
C++ Implementation of FPNN Structures
Pánek, Richard ; Čekan, Ondřej (referee) ; Krčma, Martin (advisor)
This master's thesis deals with the design and the C++ implementation of the Field Programmable Neural Networks (FPNNs) simulator. It briefly introduces the concept of artificial neural networks as it is the base of the FPNN concept. It presents the concept formal definitions and its calculation methods. The thesis also describes the special features of the FPNNs and the differences between the FPNNs and the classic neural networks. Furthermore, it deals with models of fault tolerant FPNNs. All the presented principles are used as the base of the developed implementation and the subsequent experiments.
|
|
|
Vibration sensor
Matěj, Jan ; Pristach, Marián (referee) ; Bohrn, Marek (advisor)
This Bachelor’s thesis deals with a system for reading the radar antenna gearbox vibrations. Firstly it names different types of sensors and defines their suitability for this usage. Secondly it describes the system for data transmission from transducer to computer and also explains meaning of the measured results.
|
|
|
Hardware Acceleration of Analysis and Header Field Extraction
Polčák, Libor ; Tobola, Jiří (referee) ; Kořenek, Jan (advisor)
This work deals with packet analysis and processing for high speed networks using FPGA. Model of the analysis and hardware architecture have been proposed. Protocols can be specified in XML. Automated tool is able to convert this specification to VHDL. As mul- tiple bytes and protocol headers are processed within one clock cycle simultaneously, the proposed unit is able to handle packet processing on 10 Gbps speed and higher.
|
|
|
Hardware Acceleration of Header Field Extraction
Polčák, Libor ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
Most network devices need to obtain specific packet header fields belonging to different network protocol headers for correct functionality. This work aims to create an efficient unit capable of application-specific packet header analysis and data extraction. The proposed unit deals with protocols used on L2, L3, and L4 layers of ISO/OSI model including tunneled protocols; it is possible to specify protocols which are to be supported. Data analysis is based on right linear grammar transformed to finite automaton. Hardware acceleration has to be exploited in order to achieve data processing of all traffic exchanged over high-speed networks. Using FPGA technology it is possible to achieve both fast and configurable data processing. The designed unit is able to process data on up to 40 Gbps networks. On-the-fly configuration of extracted header fields is supported.
|
|
|
Acceleration of Methods for Searching Palindroms and Repetitive Structures
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
Genetic information of all living organisms is stored in DNA. Exploring of its structure and function represents an important area of research in modern biology. One of the interesting structures occurring in DNA are palindromes. Based on the research they are expected to play an important role in interpreting the information stored in DNA, because they are often observed near important genes. Palindromes searching is complicated by the presence of mutations (changes in sequences of DNA elements), which increases the time complexity of algorithms. Therefore it is reasonable to study their parallelization and acceleration. The objective of this work is a study of palindromes searching methods and acceleration architecture design. The hardware unit implemented in a chip with FPGA technology placed on ml555 board can speed up the calculation up to 6 667 times in comparison with the best-known software method relying on suffix arrays.
|
guest ::
