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SystemVerilog Framework for DMA Controllers Verification
Zachariášová, Marcela ; Martínek, Tomáš (referee) ; Puš, Viktor (advisor)
In contemporary hardware design, verification techniques are exploited to verify the function of hardware components as well as complex systems. This thesis deals with functional verification of DMA controllers. It describes the theoretical principles of verification using the SystemVerilog language and the principles of DMA data transfer. The design of controllers is described, with the focus on design of the verification environment and results of the verification.
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Design and Implementation of the Component for Comunication with PCI Interface
Janoušek, Michal ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This masters thesis deals with design of the component facilitating communication between PCI bus and user component. Designed component is simplifying the communication protocol between designed and user components, while advanced functions of PCI bus are preserved. Target platform is COMBO6-PTM card containing FPGA with Spartan 3 technology. Communication with PCI bus is mediated by PLX component. Thesis also contains design of simplified communication protocol.
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DMA Support for HCS08 Microcontrollers Family
Novosád, Adrián ; Strnadel, Josef (referee) ; Šimek, Václav (advisor)
Embedded systems are dedicated to perform specific tasks, so design engineers can optimize them to reduce the size and cost of the product and increase the reliability and performance. However, result of these optimizations is that some architectures may lack commonly used technologies such as direct memory access (DMA). We may encounter with this situation in family of microcontrollers HCS08. The main theme of this work is to describe a design of DMA controller that can be added into the family of microcontrollers HCS08.
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High-Speed Packet DMA Transfers from FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
Computer network devices that implement data-flow monitoring to allow network manage-ment require a high-speed receiving of a large amount of data for analysis. For a deviceto enable the monitoring of a network with high data traffic, its network interface cardneeds to be capable of transferring received data to a RAM at high speed. A new mo-dule for an FPGA chip on a network interface card, which can control these transfers, wasdesigned, implemented and tested in the course of this thesis. The created module sup-ports transfer of packets from the FPGA to the computer's memory via a PCI-Express busat the speed of 100 Gb/s and 200 Gb/s. Packets are transferred by DMA in system DPDK.
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Porting Netflow/Combo6 Probe from Linux to FreeBSD
Grešša, Pavol ; Kašpárek, Tomáš (referee) ; Čejka, Rudolf (advisor)
The thesis deals with the problem of developing device drivers for FreeBSD operation system and explains particular steps necessary for their implementation. Furthermore, it describes modularity of drivers and basic technologies used in this operation system. Its purpose is to create a device driver for the principal card Combo6x of the Liberouter project. The output of the thesis should be a complete device driver supporting DMA transfers ant interrupts.
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Pultrusion process optimizing of composites based on epoxy matrix
Ostrezi, Jan ; Bábík, Adam (referee) ; Přikryl, Radek (advisor)
The theoretical part of this bachelor thesis deals with current progress in the field of long fibre reinforenced composites with matrix based on epoxy resins. It also deals with production methods of composite materials, especially pultrusion. The practical part is based on pultrusion process optimizing of composites profiles based on epoxy matrix. Profiles were examined by DMA test to set the glass transition temperature.
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High-Speed Packet Data DMA Transfers to FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Martínek, Tomáš (advisor)
This thesis deals on the design, implementation, testing and measuring of a firmware module for FPGA chips, which enables DMA transfers of network data from computer RAM to the FPGA chip placed on a network interface card. These transfers are carried out using a PCIe bus on the speed of up to 100 Gbps with the possible support of speeds 200 Gbps and 400 Gbps. The goal of this technology is to allow network data processing for the purpose of maintenance of backbone network nodes and data centers. The module is designed so it can be used on different types of FPGA chips, mainly those produced by companies Xilinx and Intel.
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Configurable SPI device
Ženčár, Pavol ; Věchet, Stanislav (referee) ; Krejsa, Jiří (advisor)
Táto práca sa zaoberá vývojom a testovaním konfigurovateľného SPI slave zariadenia, ktorého hlavným účelom je testovanie reálnych SPI master zariadení. Zariadenie je implementované pomocou STM32 mikrokontroléra na vývojovej doske NUCLEO. Medzi základné funkcionality zariadenia patrí meranie frekvencie SPI prenosu, stream mód, ktorý umožní umožní presne sledovať, čo pripojené master zariadenie posiela po SPI zbernici a LUT mód, ktorý umožňuje nakonfigurovať zariadenie tak, aby odpovedalo prednastavenými odpoveďami na aktuálnu príchodziu správu. Rozšírená funkcionalita sa skladá z EEPROM emulátor módu. V tomto móde sa zariadenia správa ako virtuálna náhrada reálneho EEPROM zariadenia. Zariadenie je pripojené k počítaču pomocou sériového portu a je možné toto zariadenie konfigurovať pomocou python programáterského rozhrania. Zariadenie taktiež hlási každú aktivitu na SPI zbernici tomuto python programátorskému rozhraniu.
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FPGA Implementation of RMAP Initiator and Target
Walletzký, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The thesis deals with design and implementation of controllers for the RMAP protocol, which is used by SpaceWire network endpoints to access memory contents of another endpoint. The theoretical research introduces concepts of the SpaceWire network, then describes the RMAP protocol and the AMBA AHB bus interface in detail. The practical part of this thesis then uses this information to design and implement controllers for the RMAP protocol. It first defines an architecture of these controllers, then describes design of individual blocks based on this architecture. As a next step, the thesis describes methods used to verify designed controllers and to test these controllers in an FPGA chip. Finally, an analysis of maximum frequency and usage of FPGA resources is done based on estimates provided by the synthesis tool.
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