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Web Based Simulator of Superscalar Processors
Majer, Michal ; Olšák, Ondřej (referee) ; Jaroš, Jiří (advisor)
A clear and interactive visualization of the superscalar processor is a valuable tool for studying its operation, particularly due to its complexity. The main contribution of this work is the extension of the existing RISC-V instruction set simulator with a new web-based user interface and improvements of the simulation quality. Nearly all modules of the simulator have been enhanced. Among other things, errors in the implementation have been resolved, statistics collection has been improved, and the instruction set has been expanded. The integration with the C language compiler is of great benefit. The simulator has been expanded to include HTTP and CLI interfaces. The React library has been utilized for implementing the web application. The result of the work is a functional and tested application, ready for practical use and with a positive impact on education.
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Improvement of the RISC-V CPU for the automotive industry
Gallo, Jiří ; Jaroš, Jiří (referee) ; Šimek, Václav (advisor)
Cílem této práce je úprava existujícího RISC-V procesoru pro použití v automobilovém průmyslu - konkrétně ovládání motorů. Tyto úpravy jsou založeny na ukázkovém kódu pro řízení motoru využívajícím aritmetiku s pevnou řádovou čárkou. Tento kód byl profilován a analyzován, na základě čehož byly vytvořeny nové instrukce. Vliv těchto instrukcí byl zanalyzován jak z pohledu zrychlení běhu, tak z pohledu dopadu na parametry procesoru.
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Implementation of system for IC testing via JTAG interface
Prášil, Pavel ; Zachariášová, Marcela (referee) ; Petyovský, Petr (advisor)
This master thesis deals with testing integrated circuits containing RISC-V processor core using JTAG protocol. This thesis objective is to design a module for 2-wire JTAG protocol support and design of an extending protocol for RISC-V processor system bus access. Designed module will be used for the integrated circuit testing using a 2-wire JTAG interface in order to reduce the number of pins dedicated for JTAG interface. The extending protocol will be used to reduce time spent by integrated circuits testing. The thesis contains description of the RISC-V testing system, design and implementation of module for 2-wire JTAG protocol support and also design and implementation of module for system bus access by the extending protocol. The thesis also includes extension of testing SW environment by support of communication using the extending protocol and verification of HW solution functionality. The thesis contain evaluation of time efficiency of implemented communication solution.
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Specialized Instruction Design
Koscielniak, Jan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The purpose of this thesis is to design and implement specialized instructions for RISC-V instruction set architecture. These instruction are used to accelerate a set of selected cryptographic algorithms. New instructions are implemented in Codasip Studio for 32bit processor model with RV32IM instruction set. Open source implementations were selected and edited to use new instructions. Instructions were used on respective algorithms, tested and profiled. The outcome of this thesis is instruction set extension, that enables up to seven times speed up, depending on used algorithm.
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Automated testbed for SIL/PIL testing of embedded application using FPGA
Prusák, Lukáš ; Burian, František (referee) ; Arm, Jakub (advisor)
The master's thesis deals with designing a testbench for a selected soft-core processor NEORV32 with a RISC-V architecture for simulations of embedded applications in an FPGA environment. The testbench was created in the Vivado environment with the aim of extending it to a testing and validation framework. Basic modules such as GPIO, PWM, UART, and PC were selected and implemented. Several test scenarios have been designed for these modules. The testbench has also been supplemented with additional scripts, to create hierarchically correct project setup and test execution. The work also suggests a few possible ways to improve and expand the testbench.
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Portable Stimulus Scenarios Specification for RISC-V Processor Modules
Bardonek, Petr ; Bidlo, Michal (referee) ; Zachariášová, Marcela (advisor)
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.
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RISC-V Processor Peripherals
Vavro, Tomáš ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
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Graphical Simulator of Superscalar Processors
Vávra, Jan ; Mrázek, Vojtěch (referee) ; Jaroš, Jiří (advisor)
Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.
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Framework for RISC-V Compliance Tests Execution
Skála, Milan ; Čekan, Ondřej (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.
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RISC-V Processor Model
Barták, Jiří ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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