|
|
Design of selected IEEE 802.1Q standard parts
Kliment, Filip ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This thesis deals with network substandards from the TSN group (IEEE 802.1Q), which deal with prioritization of network traffic in TSN networks. These sub-standards include 802.1QBV and 802.1QBU, which have been described in more detail and compared in terms of network permeability and latency. Substandard 802.1QBU was chosen for the design implementation in FPGA. The design was described in VHDL. The devloped design was verified by simulations, using self-tests. The work includes synthesis and time analysis.
|
|
|
FITkit Music Synthesizer
Melichar, Vojtěch ; Minařík, Miloš (referee) ; Vašíček, Zdeněk (advisor)
This bachelor's thesis deals with sound synthesis methods and with design of a synthesizer for FITkit platform. In the first part of the thesis, there are described methods of sound synthesis and the history of sound synthesis is also stated here. Next part contains a brief characteristic of sound chip SID 6581. In the next part of the thesis, there is a design of each part of the synthesizer: oscillator, envelope generator, voice and filter. Then, these components are put together to make up an synthesizer. Correctness of the implementation is verified by a simulation in ModelSim 6.6d. Individual components are simulated separately and then in mayor groups.
|
|
|
FITkit CAN Implementation
Jančo, Tomáš ; Janoušek, Vladimír (referee) ; Hanáček, Petr (advisor)
This thesis describes main principles of communication on CAN bus, design and implementation of CAN bus controller. The controller is implemented in VHDL for school development platform FITkit. This work also describes design of CAN physical layer circuits for connecting FITKit to CAN bus.
|
|
|
Interface for Communication on Hardware Accelerated Circuits
Slávik, Mark ; Cíbik, Peter (referee) ; Smékal, David (advisor)
The work deals with the description and implementation of the MicroSD interface on programmable logic arrays. The thesis describes the FPGA theory, VHDL language, Vivado environment,pheripherals on FPGA board, VitisHLS. Next, the implementation of the code and its simulation is described. At the end, digital image processing using FPGA and Micro SD card is explained.
|
|
|
Random Numbers Generator with Selected Distribution
Kajan, Michal ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis describes random numbers generating techniques. First part focuses on methods of obtaining pseudorandom numbers and presents typical examples of random numbers generators. This part also contains description of distribution transformation methods of random numbers and briefly deals with testing of statistical properties of random numbers generators. Following part describes LFSR generator in detail as one of most widely used generators for hardware applications. In addition, description of transformation process and implementation of circuit calculating transformation to the exponential distribution is included. Last part contains resources requierements of designed circuits for implementation in FPGA.
|
|
|
Hardware Acceleration Using Functional Languages
Hodaňová, Andrea ; Kadlček, Filip (referee) ; Fučík, Otto (advisor)
The aim of this thesis is to research how the functional paradigm can be used for hardware acceleration with an emphasis on data-parallel tasks. The level of abstraction of the traditional hardware description languages, such as VHDL or Verilog, is becoming to low. High-level languages from the domains of software development and modeling, such as C/C++, SystemC or MATLAB, are experiencing a boom for hardware description on the algorithmic or behavioral level. Functional Languages are not so commonly used, but they outperform imperative languages in verification, the ability to capture inherent paralellism and the compactness of code. Data-parallel task are often accelerated on FPGAs, GPUs and multicore processors. In this thesis, we use a library for general-purpose GPU programs called Accelerate and extend it to produce VHDL. Accelerate is a domain-specific language embedded into Haskell with a backend for the NVIDIA CUDA platform. We use the language and its frontend, and create a new backend for high-level synthesis of circuits in VHDL.
|
|
|
Methods for quadrature modulator imbalance compensation
Povalač, Karel ; Valenta, Václav (referee) ; Maršálek, Roman (advisor)
Quadrature modulator (demodulator) is used in transmitting (receiving) part of many devices. Unwanted imbalance can influence amplitude, phase or DC offset of modulator (demodulator). Correction of imbalance was a main subject of thesis. Simulations of these methods were created in MATLAB and results were compared. Basics of methods were implement on programmable logic field by program Xilinx ISE. Development kit V2MB1000 with analogue board Memec P160 was chosen for this purpose. In the last part were compare simulation results with practical measurement.
|
|
|
Construction of The GPS Devices
Hort, Marek ; Jaroš, David (referee) ; Šteffan, Pavel (advisor)
Aim of this Diploma thesis was to create a device capable of receiving navigational data from GPS. These data are subsequently stored in fixed memory and after connection with the PC are displayed it on the satellite map. The device was realized by using FPGA and GPS module LEA-5s. Description was created in the VHDL language, which was implemented into the circuit. The part of VHDL design was description of PICOBLAZE processor that controls whole system. For displaying and archiving data stored in device was created PC application GPS TRACER. It is able to display stored trace on the satellite map by using Google maps server. For created device were designed and manufactured PCBs, which were manually fitted.
|
|
|
FSO transceiver for link quality estimation
Novák, Marek ; Vlček, Čestmír (referee) ; Wilfert, Otakar (advisor)
Tato diplomová práce pojednává o zmírnění bitové chybovosti bezkabelového optického spoje s užitím principu reciprocity aplikovaného na komunikační kanál, spolu s možností kódování přenášených dat. V této práci je implementováno LDPC a Reed-Solomonovo kódování pro jejich vyhovující vlastnosti. Zbytková rámcová chybovost je vypočtena a k dispozici jako výstup systému, který je implementovaný v hradlovém poli (FPGA).
|
|
|
Application Specific Processor for Stateful Network Traffic Processing
Kučera, Jan ; Matoušek, Jiří (referee) ; Kekely, Lukáš (advisor)
This bachelor's thesis deals with the design and implementation of an application-specific processor for high-speed network traffic processing. The main goal is to provide complex system for hardware acceleration of various network security and monitoring applications. The application-specific processor (hardware part of the system) is implemented on an FPGA card and has been designed with respect to be used in 100 Gbps networks. The design is based on the unique combination of high-speed hardware processing and flexible software control using a new concept called Software Defined Monitoring (SDM). The performance and throughput of the proposed system has been verified and measured.
|
guest ::
