|
|
Hardware Accelerated Functional Verification
Zachariášová, Marcela ; Kotásek, Zdeněk (referee) ; Kajan, Michal (advisor)
Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.
|
|
|
Specialized Instruction Design
Koscielniak, Jan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The purpose of this thesis is to design and implement specialized instructions for RISC-V instruction set architecture. These instruction are used to accelerate a set of selected cryptographic algorithms. New instructions are implemented in Codasip Studio for 32bit processor model with RV32IM instruction set. Open source implementations were selected and edited to use new instructions. Instructions were used on respective algorithms, tested and profiled. The outcome of this thesis is instruction set extension, that enables up to seven times speed up, depending on used algorithm.
|
|
|
Evolutionary Analogue Amplifier Optimisation
Bielik, Marek ; Zachariášová, Marcela (referee) ; Bidlo, Michal (advisor)
Táto práca demonštruje možnosti využitia evolučných algoritmov, konkrétne evolučných stratégií, v doméne dizajnu analógových zosilňovačov. Do implementácie je zahrnutý ngSPICE simulátor, ktorý je použitý na vyhodnotenie optimalizovaných riešení a v práci je navrhnutých niekoľko vyhodnocovacích metód. Práca tiež zahŕňa experimenty a ich výsledky, ktoré boli použité na určenie najvodnejších parametrov evolučných stratégií. Cieľom bolo optimalizovať hodnoty súčiastok jedno a dvoj stupňových zosilňovačov s bipolárnymi tranzistormi v zapojení so spoločným emitorom. Výsledkom je nástroj umožňujúci návrh zosilňovačov s ľubovoľným zosilnením v rámci možností daného obvodu bez použitia akéhokoľvek matematického aparátu.
|
|
|
Coevolutionary Algorithms Statistical Analysis Tool
Urban, Daniel ; Zachariášová, Marcela (referee) ; Drahošová, Michaela (advisor)
This bachelor thesis contains a theoretical basis that introduces evolutionary algorithms, genetic programming, coevolutioanary algorithms and methods for statistical evaluation. Furthermore, this work deals with the design and implementation of tool with graphical user interface, which allows the analysis of coevolutioanary algorithm for various parameters and also its statistical evaluation. The functionality of the implemented tool has been tested on data obtained from an external program performing evolutionary design of image filters with the use of the coevolution of tness predictors. The resulting graphs and statistics allow easy comparison of the progress and results for each program run.
|
|
|
Design and Implementation of a Profiler for ASIPs
Richtarik, Pavel ; Hynek, Jiří (referee) ; Zachariášová, Marcela (advisor)
The major objective of this work is to analyse possibilities of profiling application specific instruction-set processors, to explore some common profiling techniques and to use the collected information to design and implement a new profiling tool suitable for utilization in the processors development and optimization. This bachelor thesis presents requirements on the new profiler and describes its key parts from the design and the implementation perspective.
|
|
|
Portable Stimulus Scenarios Specification for RISC-V Processor Modules
Bardonek, Petr ; Bidlo, Michal (referee) ; Zachariášová, Marcela (advisor)
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.
|
|
|
Electronic Chessboard on the FITKit Platform
Kubín, Jakub ; Zachariášová, Marcela (referee) ; Kaštil, Jan (advisor)
This thesis deals with the analysis, design and implementation of chess on FITkit platform. The platform is connected to the VGA monitor, on which is shown the chessboard with the figures. The game is controlled by using the keyboard on FITkit platform. The work describes the realisation of the unit for the display of the checkerboard that is implemented in the programmable gate field. Software of the microcontroller controls the depictive unit, generates possible moves and checks strokes of figures. There is a control whether the King does not have the check and if the game is not over because of checkmate or stalemate.
|
|
|
Assertion-Based Verification of ASIP
Šulek, Jakub ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This thesis introduces the concept of assertion-based verifi cation of application-specifi c instruction set processors (ASIPs). The proposed design is implemented in SystemVerilog Assertions language as a part of veri fication environment created using Codasip Framework. The implemented concept is simulated in QuestaSim tool using model of Codix RISC processor. Main outcome of this thesis is the verifi cation concept usable not only on other processors, but as a part of system that automates the processor design as well.
|
|
|
Extrenal Access to the proAlpha System
Suchý, Ondřej ; Zachariášová, Marcela (referee) ; Krčma, Martin (advisor)
This work deals with main goals and principles of ERP systems. On the basis of the presented principles it presents the proALPHA ERP system and examines it in order to determine external access possibilities. The external access into the proALPHA system is the main goal of this work. The materials management module has been chosen as the part of the system to be accessed. The access will be realized via proALPHA INWB module based on Sonic ESB which is described as well. All set goals of this work were reached.
|
|
| |
guest ::
RSS feed.