Original title: Verifikace ASIP založena na formálních tvrzeních
Translated title: Assertion-Based Verification of ASIP
Authors: Šulek, Jakub ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
Document type: Master’s theses
Year: 2015
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Abstract: [cze] [eng]

Keywords: application-specifi c instruction set processor; assertion-based verifi cation; SystemVerilog Assertions; veri cation environment; procesor s aplikačně-specifi ckou instrukční sadou; SystemVerilog Assertions; veri fikační prostředí; verifi kace založena na formálních tvrzeních

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/64042

Permalink: http://www.nusl.cz/ntk/nusl-603840


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2024-04-02, last modified 2024-04-03


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