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Tuned semiconductor laser for the diagnostic of the channel waveguides
Ondráček, František ; Skalský, Miroslav ; Čtyroký, Jiří
In contribution is described new measuring set up with tuned semiconductor laser and there are given first results of spectral losses and group refractive index in various channel waveguides by using a resonator method. The waveguides were prepared in special glasses by ion exchanges method and in LiNbO.sub.3./sub. crystal by proton exchange and also by titan difusion. Experimental results have demonstrated accuracy and rate of this arangement. In conclusion we have shown the possibility of the next research.
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Comparison of quantitative LIBS analysis of steel standards utilizing single-pulse and double-pulse LIBS
Pořízka, Pavel ; Hrdlička, Aleš (referee) ; Kaiser, Jozef (advisor)
In this diploma thesis the differences between single pulse and double pulse laser induced breakdown spectroscopy (LIBS) methods are discussed. The time evolution of laser induced plasma (LIP) parameters, such electron density, plasma temperature, density of ions and atoms is shown. Selected methods for evaluation of plasma parameters (Boltzmann equation, Saha-Boltzmann equation etc.) are also stated. The theoretical bases of local thermodynamic equilibrium (LTE), which is necessary condition for using of previously stated methods for computation of plasma parameters, are discussed. Diploma thesis also contains the description of each component of our LIBS experimental set up and the way of their optimization. Presented theoretical advantages of DP LIBS method are demonstrated on results of experimental measurements of steel standards.
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Development of algorithms state estimation of experimental vehicle
Lamberský, Vojtěch ; Krejsa, Jiří (referee) ; Grepl, Robert (advisor)
This thesis deals with the filter algorithm design, implementing mathematical model to improve algorithm performance. Designed algorithms are implemented in a control unit of the experimental vehicle (filters signal used in the closed-loop controller). The improvement of the position estimation using Kalman Filter is demonstrated on the experimental vehicle. In the next part the design process of algorithm developing for dsPIC microcontroller using Matlab is described.
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Tvorba mikro a nanoporů v polovodičích A.sup.3./sup. B.sup.5./sup
Nohavica, Dušan ; Gladkov, Petar ; Zelinka, Jiří ; Dvořák, Martin ; Pirov, J.
Electrochemically etched pores are accessible also in A.sup.3./sup. B.sup.5./sup. semiconductors. In particular, pores in InP, GaAs and GaP have been investigated in our laboratory. More complex experimental data have been collected for InP which is suitable for the preparation almost self organized pores net. Pores multilayer containing current oriented and/or crystallographic pores was prepared and some details of the process are discussed. The GaAs and GaP demonstrate both, current oriented and crystallographic pores as well with specific differences.
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Reamers with cermet cutting edge and PVD coating
Technik, Radim ; Humár, Anton (referee) ; Kouřil, Karel (advisor)
The Master’s thesis is focused on reaming technology using PVD coated reamers with cermet cutting edge. This work point out a historical evolution of reaming technology as well as recent requirements to the quality of produced surfaces. Reamers characteristic, splitting, mechanical designs, cutting tool geometry as well as the assumption of a reamer potential evolution are presented. Application of cermet tool material and PVD coatings to reaming tools is considered. The work contains a review of present statement at reamer market including cermet reamers and provided single cells (elements) of the Tool Management. The experimental part of the work is focused on product manufacture qualities verification of the changeable PVD coated reamer head made by HAM-FINAL ltd. Economic analysis in case of investment to the reamer purchase is demonstrated on the example of the practical application of the reamer.
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Harnessing Forest Automata for Verification of Heap Manipulating Programs
Šimáček, Jiří ; Abdulla, Parosh (referee) ; Křetínský, Mojmír (referee) ; Vojnar, Tomáš (advisor)
Tato práce se zabývá verifikací nekonečně stavových systémů, konkrétně, verifikací programů využívajích složité dynamicky propojované datové struktury. V minulosti se k řešení tohoto problému objevilo mnoho různých přístupů, avšak žádný z nich doposud nebyl natolik robustní, aby fungoval ve všech případech, se kterými se lze v praxi setkat. Ve snaze poskytnout vyšší úroveň automatizace a současně umožnit verifikaci programů se složitějšími datovými strukturami v této práci navrhujeme nový přístup, který je založen zejména na použití stromových automatů, ale je také částečně inspirován některými myšlenkami, které jsou převzaty z metod založených na separační logice. Mimo to také představujeme několik vylepšení v oblasti implementace operací nad stromovými automaty, které jsou klíčové pro praktickou využitelnost navrhované verifikační metody. Konkrétně uvádíme optimalizovaný algoritmus pro výpočet simulací pro přechodový systém s návěštími, pomocí kterého lze efektivněji počítat simulace pro stromové automaty. Dále uvádíme nový algoritmus pro testování inkluze stromových automatů společně s experimenty, které ukazují, že tento algoritmus překonává jiné existující přístupy.
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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Methodology of highly reliable systems design
Straka, Martin ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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