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Specialized Computer System Automatic Control
Opálka, Jan ; Šátek, Václav (referee) ; Kunovský, Jiří (advisor)
This work deals with the automatic control of calculations of specialized system. The reader is acquainted with the numerical solution of differential equations by Taylor series method and numerical integrators. The practical aim of this work is to analyze parallel characteristics of Taylor series method, specification of parallel math operations and design of control of this operations.
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Fractional-Octave Analysis of Acoustic Signals
Ryšavý, Marek ; Frenštátský, Petr (referee) ; Schimmel, Jiří (advisor)
The diploma thesis is focused on design and optimalization of digital octave and fraction-octave band filters. This thesis describe the behavior of filters in systems with fixed point arithmetics and investigate the impact of quantization coefficients for frequency response of filter. Filters, whitch has been designed, are implemented into simple software in C. Designed filters are in accordance with standard IEC 61260.
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Implementation of fixed-point arithmetic unit in FPGA
Kalocsányi, Vít ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with a design of fixed-point arithmetic unit for FPGA circuits and its model in Matlab. The thesis explains a number representation in digital circuits and both basic and selected additional arithmetic operations with fixed-point numbers. The arithmetic unit’s model is designed in Matlab, the realization of the unit in VHDL is described and its implementation into FPGA is carried out. A specific example of use of designed arithmetic unit’s model for simulation of complex systems in Simulink environment is shown at the end of the thesis.
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FPGA implementation of artificial neural network
Čermák, Justin ; Šteffan, Pavel (referee) ; Bohrn, Marek (advisor)
This master's thesis describes the design of effective working artificial neural network in FPGA Virtex-5 series with the maximum use of the possibility of parallelization. The theoretical part contains basic information on artificial neural networks, FPGA and VHDL. The practical part describes the used format of the variables, creating non-linear function, the principle of calculation the single layers, or the possibility of parameter settings generated artificial neural networks.
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Loading and Printing ASCII Numbers in FPGA
Závodník, Tomáš ; Zachariášová, Marcela (referee) ; Bartoš, Václav (advisor)
The topic of this work is the issue of processing decimal numbers using binary hardware units. Making use of specialized hardware for this purpose is problematic due to both number systems being incompatible. The thesis is focused specifically on fixed point decimal numbers passed in the form of ASCII character strings and on the FPGA technology. The proposed solution lies in creating hardware units that allow sequential loading and printing of decimal numbers in the mentioned form digit by digit. In terms of the content of this work, it introduces suitable algorithms and describes the realization of the proposed units. It results in their efficient, configurable, portable and reusable implementation.
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A Library for Convolutional Neural Network Design
Rek, Petr ; Mrázek, Vojtěch (referee) ; Sekanina, Lukáš (advisor)
In this diploma thesis, the reader is introduced to artificial neural networks and convolutional neural networks. Based on that, the design and implementation of a new library for convolutional neural networks is described. The library is then evaluated on widely used datasets and compared to other publicly available libraries. The added benefit of the library, that makes it unique, is its independence on data types. Each layer may contain up to three independent data types - for weights, for inference and for training. For the purpose of evaluating this feature, a data type with fixed point representation is also part of the library. The effects of this representation on trained net accuracy are put to a test.
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SSI Dividing Numerical Integrator
Suntcov, Roman ; Veigend, Petr (referee) ; Šátek, Václav (advisor)
The thesis deals with numerical integration and hardware division operations. The reader is familiar with the numerical solution of differential equations through several different methods, for example Taylor's series. Furthermore, it is discussed the operation of division in the hardware and the method of its implementation in the FPGA. Subsequently, a parallel-parallel and serial-parallel integrator is designed. The practical aim of the thesis is to design and implement a serial-serial dividing integrator and create a simulator for it.
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Audio equalizer implementation based on FPGA structure
Otisk, Libor ; Valach, Soběslav (referee) ; Kváš, Marek (advisor)
The bachelor thesis introduces the basic types of audio equalizers. It describes the design of digital filters for graphic equalizer, the correct choice of structure, placement and shape of digital filters. It also describes the implementation of graphic equalizer in the fixed-point arithmetic. It further describes an implementation of the algorithm graphic equalizer on PC and the implementation in gate array of FPGA.
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Simulation tool for fixed-point arithmetic
Grézl, Vojtěch ; Kunz, Jan (referee) ; Čala, Martin (advisor)
This bachelor's thesis is focused on creating tool for simulating calculations with fixed point. This tool simplifies and increases the efficiency of performing operations with values of different data types. By calculating and graphically displaying absolute errors, which creates a conversion of values between data types and conversion through maximum absolute errors, the user can evaluate whether this conversion is optimal or not. After getting acquainted with this issue in the theoretical introduction part, the design of the practical part follows, which summarizes the implementation and procedure of program design in the LabVIEW 2021. Process of draft of the practical part is based on attributes of LabVIEW and it’s part FPGA module and aim on creating of transparent and user-friendly user interface. The output of the practical part is a tool that works with the created VI, containing a sequence of different operations with different input and output data types. The program is used to convert numbers of different data types to another type, mainly for a conversion to a fixed point data type. The user gives the main direction by creating a sample VI, the operations of which will then be performed. Other parameters that the user can set and affect the program are listed on the user interface.
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Implementation of fixed-point arithmetic unit in FPGA
Kalocsányi, Vít ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with a design of fixed-point arithmetic unit for FPGA circuits and its model in Matlab. The thesis explains a number representation in digital circuits and both basic and selected additional arithmetic operations with fixed-point numbers. The arithmetic unit’s model is designed in Matlab, the realization of the unit in VHDL is described and its implementation into FPGA is carried out. A specific example of use of designed arithmetic unit’s model for simulation of complex systems in Simulink environment is shown at the end of the thesis.
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