National Repository of Grey Literature 49 records found  previous11 - 20nextend  jump to record: Search took 0.00 seconds. 
Simulator of SCADA protocols
Bohačík, Antonín ; Mlýnek, Petr (referee) ; Blažek, Petr (advisor)
This work is focused on creation of fully functional communication generator of IEC 60870-5-104 protocol. The theoretical part explains in detail the basic principles, properties and possibilities of communication standards DNP3, IEC 60870 and IEC 61850. The next part is focused on the analysis of communication and implementation of this communication in the PQ MEg44PAN device. The last part deals with the configuration of Raspberry Pi 3 devices and the communication emulation of the IEC 60870-5-104 protocol. All programs were written and tested using the Clion development environment.
Java Byte Code Emulator Suitable for Malware Detection and Analysis
Kubernát, Tomáš ; Rogalewicz, Adam (referee) ; Drahanský, Martin (advisor)
The goal of this thesis is to create a virtual machine that emulates a running programs written in Java programing language, which would be suitable for malware analysis and detection. The emulator is able to detect arguments of exploitable methods from Java standard classes, the order of calling these exploitable methods and also execution the test application. Overall functionality was tested on appropriate examples in which held its own measurements. At the end of the paper we describe testing of the emulator, which also contains tables and graphs for better results visualization.
Virtualization of laboratory tasks for the CISCO course
Abbasi, Farhad ; Komosný, Dan (referee) ; Kubánková, Anna (advisor)
Tato bakalářská práce se zabývá laboratorními úlohami pro novou certifikaci CISCO (CCNP ENARSI), seznámením se s tématy, výběrem nejvhodnějšího prostředí pro simulaci laboratorních úloh, vytvořením topologie pro každou laboratoř. Kromě topologie byl vytvořen konfigurační soubor (.txt) a nahrán do příslušného zařízení pro úlohy zaměřené na hledání problémů. V neposlední řadě bylo navrženo a implementováno řešení vzdáleného přístupu pro připravené laboratoře.
A CPU Emulator for Course of Assembly Languages
Charvát, Lukáš ; Samek, Jan (referee) ; Smrčka, Aleš (advisor)
The master thesis discusses the design of an emulator of a CPU architecture instruction set aimed at assembly languages course. While most of nowadays emulators are architecture specific, the emulator proposed in master thesis aims at education and better understanding of assembly languages. The emulator is not limited to a single CPU, but it easily allows defining a purpose-specific architecture and instruction set in order to perform operations upon it and to display its current state.
Design of a wireless communication interface with a PC for an emulation platform for modeling integrated circuits
Benc, Marek ; Janůš, Tomáš (referee) ; Šteffan, Pavel (advisor)
In the design center of Onsemi in Rožnov pod Radhoštěm, they use an emulation platform based around an FPGA for verification and debugging tasks for certain integrated circuits, and it's equipped with an interface that models an IC's configuration fuses with physical switches. For ICs with large fuse counts, working with this interface is tedious and error-prone, which has lead to this thesis investigating the possibilities for creating a wireless configuration interface that would be controlled by a PC.
Emulation of Memory Subsystems in Multiprocessor Environment
Rajčok, Andrej ; Husár, Adam (referee) ; Přikryl, Zdeněk (advisor)
This study cover problem of design of emulation platform for multiprocesors systems. This study discuss problem of multiprocessor communication, it discuss different kind of communication systems for multiprocesor communication and protocols for data coherency. One of the solutions is picked, and the design is made and implemented into integrated design enviroment. In the end, study analyze created emulation system with focus on performance and memory load.
Low-power emulators of higher-order elements
Teska, Tomáš ; Brzobohatý, Jaromír (referee) ; Biolek, Dalibor (advisor)
The thesis deals with emulating higher-order elements using the transformation mutators, which were described by Leon Chua in 1971. The procedure of designing mutators from their mathematical description to the synthesis of concrete electrical circuits is described. The circuit solutions are based on the utilization of advanced circuit principles in order to achieve optimal circuit performance. Mutators are implemented as a set of eight incremental modules. Via their cascade connection, it is possible to emulate arbitrary elements from the periodical table of higher-order elements. The proposed solutions are tested by means of computer simulations and also verified by measurements.
Emulator of Amiga A500 Home Computer in FPGA
Biberle, Zdeněk ; Strnadel, Josef (referee) ; Šimek, Václav (advisor)
This work takes a look at existing hardware reimplementations of the Amiga 500 home computer and examines the possibility of implementing a similar solution based on the Minerva a and Pipistrello development platforms. The result of this work is an emulator od the Amiga 500 based on a combinator of both platforms.
User interface emulator of thermoregulator
Viták, Jan ; Šír, Michal (referee) ; Bradáč, Zdeněk (advisor)
The aim of this bachelor thesis User Interface Emulator of Thermoregulator is to design a concept of the emulator and to implement the emulator including the software. The thesis includes description of the thermostat and the particular sensors emulated, the designed concept of the system, description of the designed circuitry and the description of the embedded software and the control software for PC. The design of circuit diagram of the emulator and the design of printed circuit board are in the attachment of this thesis.
Unified verification environment for digital part of automotive mixed-signal integrated circuits
Petráš, Samuel ; Dvořák, Vojtěch (referee) ; Prokop, Roman (advisor)
This thesis is concerned with unified verification environment for the verification of small designs of the digital part of integrated circuits with mixed signals. By unified verification environment is meant an environment suitable for both simulation and emulation. The first chapter describes the current verification methods of such designs. The second chapter presents the requirements that emulation places on the verification environment implemented according to the Universal Verification Methodology (UVM) and the attached implementation of proposed environment. The third chapter contains practical knowledge gained during the implementation of the unified verification environment, problems and their solutions, as well as several comparisons between simulation and emulation.

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