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Hardware Accelerating of Encryption Algorithm
Hradil, David ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
The goal of this thesis is to design a hardware realization of circuit which will implement the AES algorithm. A motivation was to make an acceleration against the classic software encryption. The acceleration is achieved by special designed parts of the circuit, which correspond to particular operations of the AES algorithm. First, there was necessary to design the circuit. In the next step there was a need to describe the designed circuit by the VHDL language. Then the circuit was simulated and synthesized. Due to comparing the circuit with software processing a software implementation was created. Both implementations were created for the FITKit platform. The hardware implementation is made by the FPGA technology and the software implementation is realized in a microcontroller. The result of the thesis is almost one thousandfold acceleration against the classic software encryption.
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AES Tolerance to Timing Analysis
Ondruš, Juraj ; Matyáš, Václav (referee) ; Cvrček, Daniel (advisor)
This thesis deals with timing analysis of the AES (Advanced Encryption Standard). The design of {\em Rijndael\/}, which is the AES algorithm, is described here. For the side channel attacks is necessary to know the principles of the cache memory in CPU and its architecture. In this thesis are involved major security problems of AES which can be used for successful attacks. Several different implementations of AES are discussed too. Several types of timing attaks are also described. According to the experimentations these attacks should be efficient to the most presently used AES implementations. Finally, the results of this work are described, possible countermeasures against this attack and motions for the next research.
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FITkit - PC Crypted Communication
Kouřil, Miroslav ; Strnadel, Josef (referee) ; Růžička, Richard (advisor)
This thesis deals with the issue of concealing confidential data being transmitted in between two systems. The coding standard AES as a block symmetric cipher has been selected. In practise, the connection between the FITkit platform and a PC was set via serial communication. The FITkit is programmed in language C and the PC in language C++ . There has been designed a simple protocol for setting up the connection and for the information exchange about encoding. Due to the difficulties with serial communication on the kit side there have been created two applications. The first application reads encoded kit data and translates them with the assistance of preset values. The second one communicates with the kit emulator on the other computer and works at full range, what means - establishing the connection, generating keys modes and number of encoding rounds, safe key exchange and the possibility of data reading and writing to the kit.
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Encrypted Communication between Two FITkits
Bořutík, Stanislav ; Kajan, Michal (referee) ; Žádník, Martin (advisor)
This thesis is about encrypted communication between two FITkits. Thesis goal is implementation of system for short text message one-way transmission through RS-232 interface. Messages are encrypted by AES-128 algorithm working in CBC mode and their input and display are provided by keyboard and LCD display of FITkit device.
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Algebraická teorie S-boxů
Ďuránová, Elena ; Tůma, Jiří (advisor) ; Drápal, Aleš (referee)
The thesis focuses on an algebraic description of S-boxes by the special type of quadratic equations, defined as biaffine equations. Biaffine equations satisfying S-boxes of higher order may not even exist. However, the special type of S-boxes en- ables to find such equations also for S-boxes of higher order. The S-box in the block cipher Rijndael, composed of the inverse function and the affine transformation, is an example of such special type of S-boxes. The thesis proves that a number of biaffine equations satisfying an S-box of this type does not depend on the affine function. The thesis also proves that for every S-box of order n formed by the in- verse function there exist at least 3n − 1 biaffine equations satisfying this S-box. 1
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FITkit - PC Crypted Communication
Kouřil, Miroslav ; Strnadel, Josef (referee) ; Růžička, Richard (advisor)
This thesis deals with the issue of concealing confidential data being transmitted in between two systems. The coding standard AES as a block symmetric cipher has been selected. In practise, the connection between the FITkit platform and a PC was set via serial communication. The FITkit is programmed in language C and the PC in language C++ . There has been designed a simple protocol for setting up the connection and for the information exchange about encoding. Due to the difficulties with serial communication on the kit side there have been created two applications. The first application reads encoded kit data and translates them with the assistance of preset values. The second one communicates with the kit emulator on the other computer and works at full range, what means - establishing the connection, generating keys modes and number of encoding rounds, safe key exchange and the possibility of data reading and writing to the kit.
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Encrypted Communication between Two FITkits
Bořutík, Stanislav ; Kajan, Michal (referee) ; Žádník, Martin (advisor)
This thesis is about encrypted communication between two FITkits. Thesis goal is implementation of system for short text message one-way transmission through RS-232 interface. Messages are encrypted by AES-128 algorithm working in CBC mode and their input and display are provided by keyboard and LCD display of FITkit device.
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|
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AES Tolerance to Timing Analysis
Ondruš, Juraj ; Matyáš, Václav (referee) ; Cvrček, Daniel (advisor)
This thesis deals with timing analysis of the AES (Advanced Encryption Standard). The design of {\em Rijndael\/}, which is the AES algorithm, is described here. For the side channel attacks is necessary to know the principles of the cache memory in CPU and its architecture. In this thesis are involved major security problems of AES which can be used for successful attacks. Several different implementations of AES are discussed too. Several types of timing attaks are also described. According to the experimentations these attacks should be efficient to the most presently used AES implementations. Finally, the results of this work are described, possible countermeasures against this attack and motions for the next research.
|
|
|
Hardware Accelerating of Encryption Algorithm
Hradil, David ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
The goal of this thesis is to design a hardware realization of circuit which will implement the AES algorithm. A motivation was to make an acceleration against the classic software encryption. The acceleration is achieved by special designed parts of the circuit, which correspond to particular operations of the AES algorithm. First, there was necessary to design the circuit. In the next step there was a need to describe the designed circuit by the VHDL language. Then the circuit was simulated and synthesized. Due to comparing the circuit with software processing a software implementation was created. Both implementations were created for the FITKit platform. The hardware implementation is made by the FPGA technology and the software implementation is realized in a microcontroller. The result of the thesis is almost one thousandfold acceleration against the classic software encryption.
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