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Porting NetCOPE Platform to EDK
Palička, Jan ; Košař, Vlastimil (referee) ; Viktorin, Jan (advisor)
This bachelor's thesis deals with porting of NetCOPE to Xilinx Embedded Development Kit (EDK). Main task is to create annotation of NetCOPE hardware for using in EDK. Before implementation of annotation itself, it is necessary both to study FPGA technology, possibilities of FPGA progamming, NetCOPE platform and PSF for anotation of NetCOPE’s IP-core.
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Packet generator on the FPGA platform
Bari, Lukáš ; Blažek, Petr (referee) ; Smékal, David (advisor)
The thesis deals with the theory and design of the network traffic generator on the FPGA platform. The VHDL programming language is used for the description. The work involves getting acquainted with the development processes and design tools needed to create the overall project. It also includes familiarity with the necessary FPGA, NetCOPE and COMBO cards. Based on this information, was designed, tested and implemented packet generator project for the Combo-80G card. For implementation was used framework from NetCOPE.
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Design and implementation of Twofish cipher on the FPGA network card
Cíbik, Peter ; Martinásek, Zdeněk (referee) ; Smékal, David (advisor)
This bachelor thesis deals with implementation of block cipher Twofish on the FPGA platform in VHDL language. The teoretical introduction explains basics of cryptography and symetric ciphers block operation modes, FPGA platform and introduction to VHDL language. In the next part the Twofish cipher, its components and flow are being dis- cussed in depth. Subsequently describes design of Twofish cipher in VHDL language and induvidual steps in this process. The last part deals with own implementation on hardware card with FPGA chip and summarizes reached goals.
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Implementation and Verification of Network Interface Blocks
Matoušek, Jiří ; Kaštil, Jan (referee) ; Tobola, Jiří (advisor)
Network interface blocks are basic part of the NetCOPE platform where they help to the network application designers to deal with problems of implementing the Data Link Layer of the OSI Reference Model, especially the MAC sublayer. This thesis is focused on the design and implementation of such network interface blocks operating at speed 10 Gb/s. Designed input interface block provides checking of several parts of the Ethernet frame and allows discarding of this frame based on checking results. Output interface block supports replacing frame's Source Address by a pre-set value and provides frame's CRC computation. Both network interface blocks also include a set of frames counters. Implemented network interface blocks were tested on the COMBO card. SystemVerilog verification testbench was also designed for both network interface blocks.
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Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
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Routing in High-speed Computer Networks
Vlček, Lukáš ; Hanák, Pavel (referee) ; Škorpil, Vladislav (advisor)
Goal of this master thesis is to introduce and bring up basics and principles of NetCOPE framework in many details using "first approach" method for exploration of its internal structures - mainly focusing on application core using VHDL for focus itself. Furthermore, this knowledge is used for design and implementation of filtration system for network traffic with more details within phase of design in VHDL language.
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Stateful Firewall for FPGA
Žižka, Martin ; Kajan, Michal (referee) ; Puš, Viktor (advisor)
This thesis describes the requirements analysis, design and implementation of stateful packet filtering to an existing stateless firewall. They also deals with testing of the implemented system. The first two chapters describe the properties NetCOPE development platform for FPGA. They also describes the principle of operation firewall, which also serves as a requirements specification for stateful firewall. Then describes the detailed design of individual modules to modify the existing firewall and the proposal for the creation of new modules. It also discusses the implementation of the proposed modules and testing for proper operation. Finally, it discuss the current state of the thesis and describes possible future expansion.
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P4 cryptographic primitive support
Cíbik, Peter ; Malina, Lukáš (referee) ; Smékal, David (advisor)
This diploma thesis deals with the problem of high-speed communication security which leads to the usage of hardware accelerators, in this case high-speed FPGA NICs. Work with simplification of development of FPGA hardware accelerator applications using the P4 to VHDL compiler. Describes extension of compiler of cryptographic external objects support. Teoretical introduction of the thesis explains basics of P4 language and used technologies. Describes mapping of external objects to P4 pipeline and therefore to FPGA chip. Subsequently deals with cryptographic external object, compatible wrapper implementation and verification of design. Last part describes implementation and compiler extension, cryptographic external object support and summarizes reached goals.
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Platform for Rapid Development of Network Devices
Tobola, Jiří ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis deals with the design and implementation of an FPGA-based platform for rapid development of network applications for the COMBO cards family. The proposed platform includes a generic data transfer protocol - FrameLink, a set of tools for FrameLink manipulation, network interface blocks for 1 Gigabit Ethernet, high-speed connection to the software layer via PCI, PCI-X or PCI Express bus and a set of IP cores for network traffic analysis and processing. The benefits of the proposed platform are demonstrated on design and implementation of a network interface card, hardware firewall and exporter of unified packet headers.
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