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Implementation of Digital Circuit for High-Speed Network Communication in FPGA
Kondys, Daniel ; Cíbik, Peter (referee) ; Smékal, David (advisor)
Vysokorychlostní síťové karty často obsahují prvky pro hardwarovou akceleraci, která jim umožní efektivně zpracovávat data i při velmi vysokých rychlostech. Tato práce se zabývá tvorbou digitálního obvodu pro FPGA, který bude přenášet Ethernetové rámce rychlostí až 400 Gb/s. K tomu využívá bloky duševního vlastnictví pro Ethernet, které jsou součástí moderních FPGA čipů od firmy Intel. Jedná se o FPGA Stratix 10, které obsahuje bloky duševního vlastnictví typu E-tile, a Agilex, které obsahuje bloky duševního vlastnictví typu F-tile. Před vlastním návrhem se práce zabývá teoretickým rozborem standardu Ethernet a činnostmi jednotlivých podvrstev, popisuje vybrané FPGA čipy a zabývá se i NDK platformou, do níž bude vytvořený obvod zapojen. Praktická část spočívá v konfiguraci daných duševních bloků pro Ethernet a jejich integrací do vytvářeného obvodu. Nakonec jsou popsány metody pro ověření funkčnosti vytvořeného obvodu. Ty zahrnují verifikaci a testy na platformách s danými FPGA čipy. Výsledky ukazují, že vytvořený obvod je funkční a dosahuje rychlosti i 400 Gb/s. Jeho využití spočívá zejména v poskytnutí komunikace přes Ethernet pro digitální obvod, který bude dodáván jako součást firmwaru pro síťovou kartu XpressSX AGI-FH400G vyvinutou sdružením CESNET z.s.p.o a společností REFLEX CES.
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Implementation of Simple Speech Recognizer in Android
Flajšingr, Petr ; Herout, Adam (referee) ; Szőke, Igor (advisor)
The subject of this thesis is an implementation and optimization of speech recognizer for operating system Android. This work covers implementation of recording of an audio signal and the subsequent feature extraction using Mel filter banks and neural network. It also contains information about implementation of dynamic decoder. The work focuses on implementation in low-level tools such as Android NDK and Renderscript and evaluates the success rate of the recognizer and its memory and time requirements.
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Implementation of Simple Speech Recognizer in Android
Čuba, Eduard ; Glembek, Ondřej (referee) ; Szőke, Igor (advisor)
The goal of this project is to implement speech recognition software for Android platform. This paper outlines fundamental components of a speech recognizer and reviews the techniques used to optimize the process of speech recognition on Android devices. Firstly, it examines the implementation of the acoustic feature extraction and phoneme estimation processes. Then, it describes the design and implementation of a decoder used to process phoneme estimations into transcription, utilizing only limited resources of a mobile device. The project is divided into several modules, forming an Android library, which should be easy to extend and can be provided with custom models tailored for the desired use. Later, this paper discloses various approaches to modeling abstract data structures for recognition network representation, as well, as the ways of further development and applications of this project.
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Prototyping of Photographic Composition Using Augmented Reality
Salát, Marek ; Szentandrási, István (referee) ; Herout, Adam (advisor)
The thesis deals with an image processing problem called image matting. The problem involves detection of a foreground and background in an image with minimal user interaction using trimaps. Foreground detection is used in image composition. The goal of the thesis is to apply already known algorithms, in this case A Global sampling matting, in an Android application. The most important result is an intuitive application that can be used for making creative viral photos. Agile methodology is applied throughout the whole application development cycle. From the very beginning, the application is publicly available as a minimum viable product on Google play. The work’s contribution is in optimization of the mentioned algorithm for use in mobile devices and parallelization on a GPU, together with a publicly available application.
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Object Detection Algorithms on Android Platform
Dlápal, Vojtěch ; Musil, Martin (referee) ; Musil, Petr (advisor)
Aim of this thesis is to analyze possibilities of object detection on Android platform, design demonstrative application, test it and evaluate results. Android platform, computer vision library OpenCV and object detection theory are being introduced. Application for comparison of face detection from OpenCV, Android API and custom detector using classifier was designed and implemented. Application was tested and the results were evaluated.
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Mobile Video Manual with Automatic Object Recognition
Nedbálek, Stanislav ; Maršík, Lukáš (referee) ; Španěl, Michal (advisor)
This thesis deals with potential of us computer vision and augmented reality on mobile platform - OS Android. The goal of this thesis is to demonstrate practical potential of mentioned technologies on nowdays real situations. This thesis aims to design and implementation of mobile application, which is able to show video manual for automatic detected object. The created application has been tested on group of users, which approved useability and intuitivness of this application.
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FPGA Digital Circuit for up to 400 Gbps Transfers over Ethernet
Kondys, D. ; Smékal, D.
Network cards with a hardware acceleration feature are a popular solution for meeting the ever-increasing demands for throughput in high-speed networks. Utilizing the FPGA (Field Programmable Gate Array) chips as the hardware acceleration elements, this paper presents a generic and highly modular digital circuit for FPGA that manages the transfer of data in form of Ethernet frames at rates reaching up to 400 Gbps. To achieve this, the proposed digital circuit takes advantage of the Ethernet intellectual property (IP) blocks in high-end FPGAs from Intel. By first implementing and fine-tuning it for data rates up to 100 Gbps, the next step is expanding it to reach data rates up to 400 Gbps. The created digital circuit will then be used in the FPGA design for the XpressSX AGI-FH400G network card (among others) created by companies CESNET a.l.e and REFLEX CES. Even though the target data rate is 400 Gbps, this paper focuses on the first step, which is the utilization of the Intel Ethernet hard IP blocks to reach 100 Gbps.
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Anonymous certificates for user authentication
Hlinka, Jan ; Malina, Lukáš (referee) ; Dzurenda, Petr (advisor)
Topic of this thesis is privacy protection when using anonymous certificate authentication. Today’s most common case of oversharing private data is proving Covid vaccination or Covid test results. This thesis describes and implements system that is using anonymous certficates. The system solves mentioned issues of current CovidPass authentication methods. The implementation is done on the Android platform in case of the user application and verifier application is run on Raspberry PI, which works as an access terminal.
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Cryptographic algorithms on FPGA
Broda, Jan ; Jedlička, Petr (referee) ; Hajný, Jan (advisor)
The master thesis is focused on developing a demonstrator which is able to transmit data not only between operating system and network FPGA card with a UltraScale+ chip but also between two network FPGA cards. The theoretical part of the master thesis describes FPGA, developing on FPGA, programming languges that are used and develoment enviroment Vivado Design Suite. The demonstrator consists of two applications developed in C language which are used for communication between operating system and the network FPGA card and two components developed in VHDL langague which are used for communication throught a network module on the network FPGA card. The demonstrator allows inserting cryptographic algorithm which would work with transmitted data. For developing on the network FPGA card was used a Network Development Kit provided by a Liberouter team from CESNET association.
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Implementation of Digital Circuit for High-Speed Network Communication in FPGA
Kondys, Daniel ; Cíbik, Peter (referee) ; Smékal, David (advisor)
Vysokorychlostní síťové karty často obsahují prvky pro hardwarovou akceleraci, která jim umožní efektivně zpracovávat data i při velmi vysokých rychlostech. Tato práce se zabývá tvorbou digitálního obvodu pro FPGA, který bude přenášet Ethernetové rámce rychlostí až 400 Gb/s. K tomu využívá bloky duševního vlastnictví pro Ethernet, které jsou součástí moderních FPGA čipů od firmy Intel. Jedná se o FPGA Stratix 10, které obsahuje bloky duševního vlastnictví typu E-tile, a Agilex, které obsahuje bloky duševního vlastnictví typu F-tile. Před vlastním návrhem se práce zabývá teoretickým rozborem standardu Ethernet a činnostmi jednotlivých podvrstev, popisuje vybrané FPGA čipy a zabývá se i NDK platformou, do níž bude vytvořený obvod zapojen. Praktická část spočívá v konfiguraci daných duševních bloků pro Ethernet a jejich integrací do vytvářeného obvodu. Nakonec jsou popsány metody pro ověření funkčnosti vytvořeného obvodu. Ty zahrnují verifikaci a testy na platformách s danými FPGA čipy. Výsledky ukazují, že vytvořený obvod je funkční a dosahuje rychlosti i 400 Gb/s. Jeho využití spočívá zejména v poskytnutí komunikace přes Ethernet pro digitální obvod, který bude dodáván jako součást firmwaru pro síťovou kartu XpressSX AGI-FH400G vyvinutou sdružením CESNET z.s.p.o a společností REFLEX CES.
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