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FFT implementation in FPGA and ASIC
Dvořák, Vojtěch ; Bohrn, Marek (referee) ; Fujcik, Lukáš (advisor)
The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
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Measurement parameters of communication via PCI Express
Dujiček, Ondřej ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This bachelor thesis deals with parameters affecting throughput of PCI Express bus and its main result is a design and implementation of a unit for measuring parameters of communication over PCI Express bus. The unit is implemented in VHDL language and its support on generating and measuring traffic at speeds up to 100 Gbps. Unit’s operation frequency, when implemented in Virtex 7 available at COMBO-100G , is 200 MHz. The implemented unit is controlled from software through MI32 interface and it is able to measure the amount of transferred packets and data in both receive and transmit directions. This information can be exported into software using MI32 interface.
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A Test Interface for Integrated Circuits with the Small Number of Pins
Tománek, Jakub ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.
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IP core for BLDC motor control
Hráček, Marek ; Bohrn, Marek (referee) ; Dvořák, Vojtěch (advisor)
This diploma thesis is about using vector control (or field-oriented control) of synchronous BLDC and PMSM motors on FPGAs. First part describes basic theory of these motors and how to control them. Then vector control is detailed and its parts as (or Clarke) and Park transformation. Rest of the thesis deals with the design of universal controller with adjustable accuracy in VHDL language. Data is separated from computing part which utilizes custom arithmetic-logic unit. In the last part of the thesis the design is tested in simulator using model of PMSM motor.
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METAPHYSICAL STORIES
Dvořák, Vojtěch ; Písařík, Petr (referee) ; Rathouský, Luděk (advisor)
The work entitled "Metaphysical stories" relates to the personal perception and experience of the outside world and oneself, as well as to the perception of painting and picture. The concept of metaphyisics is borrowed from philosophy precisely for its thematization of human existence. The narrative presents a stream of expressions intended for sharing, communication, entertainment and learning. The bachelor thesis consists of a series of oil paintings on canvas. These are abstract paintings in which I examine the shape, color and subject matter of the painting. Imaginative scenes devoid of figures and perspectives. The aim is to open up as much space as possible to unlimited expression.
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Implementation of modular arithmetic in FPGAs and ASICs
Sýkora, Michal ; Bohrn, Marek (referee) ; Dvořák, Vojtěch (advisor)
This thesis is focused on analysis, design and implementation of modular arithmetic in FPGAs and ASICs. Its main objective is to create a C++/SystemC library, that contains synthesizable functions for operations with Montgomery reduction in modular arithmetic. Results of the implementation of Montgomery reduction are compared with results of classic algorithms for modular arithmetic.
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AUTOMATED TESTING OF 10GbE DEVICES
Avramović, Nikola ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Tato práce se zabývá návrhem modelu pro funkční verifikaci a návrhem syntetizovatelného testru 10Gb Ethernet zařízení, které používají XGMII rozhraní. Pro popis modelu je použit programovací jazyk VHDL. Práce zahrnuje vytváření bus functional modelu a návrh testru, který se implementuje jako genericky self-test modul. Výsledný návrh umožňuje verifikaci a testování PHY a MAC vrstve. Pro implementaci testru byla použita vývojová deska DE5-Net osazena FPGA obvodem Stratix V GX od firmy Altera.
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