National Repository of Grey Literature 99 records found  beginprevious31 - 40nextend  jump to record: Search took 0.00 seconds. 
Modelling of PowerPC Processor
Blaha, Hynek ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Processor architectures are becoming increasingly complex, so great emphasis is put on the automation of their desings. This bachelor thesis describes the design of the PowerPC processor architecture in Codal language. The model is created according to avaliable documentation. The functionality and efficiency of the model was verified by tests provided by research group Lissom and compared to current competitor.
The acquisition system for surface electromyography
Milek, Jakub ; Sekora, Jiří (referee) ; Janoušek, Oto (advisor)
At the beginning of this work the physiological nature of electromyographic signal is described. Design of miniature, portable EMG amplifier for surface measurement is presented. Creation of program for data visualization is described, followed by description of practical EMG amplifier realization.
Real Time Recorder of Events
Nezval, Tomáš ; Kosina, Petr (referee) ; Šandera, Josef (advisor)
In this bachelor project I have been working on the design and construction of a device for storing 8 bits information on a SD/MMC memory card. The main problems are: storing of data on a memory card by microcotroller PIC in a way that will be readable on a PC (TXT file); implementation of file system FAT16; storing the data in defined time intervals by RTC (real time circuit), and ensuring the overall design enables minimal consumption of the battery power supply.
Processor Models Creation Using ADL Language
Steinhauser, Dominik ; Hynek, Jiří (referee) ; Hruška, Tomáš (advisor)
Goal of this bachelor thesis is to create instruction level models of two processors Tensilica Xtensa and Sparc Leon. Models were implemented in CodAL language. Development, simulation and testing took place in Codasip Studio, an IDE developed by Codasip company. Application Specific Instruction-Set Processors can be implemented from scratch or already implemented processor can be modified to meet needs of specific aplication. My models will be added to portfolio of Codasip company to be used and modified by the user of Codasip Studio. Result of this work are tested models of these two processors. Simulator, assembler and C language compiler of these processors can be generated. Models were compared by several Benchmark tests and results were analyzed.
C Language Compiler Back-End for PicoBlaze-6
Bříza, Martin ; Ďurfina, Lukáš (referee) ; Křivka, Zbyněk (advisor)
Tato práce řeší konstrukci zadní části kompilátoru jazyka C pro soft-core procesor PicoBlaze-6 od firmy Xilinx. K řešení tohoto problému bylo zvoleno užití projektu Small Device C Compiler coby přední části překladače. Vytvořené řešení poskytuje podporu volání ukazatelů na funkce a užití struktur. Hlavním přínosem této práce je přenesení pokročilých konstrukcí jazyka C na procesor PicoBlaze.
Processors Library for the Embedded System Design
Zvonček, Radovan ; Husár, Adam (referee) ; Hruška, Tomáš (advisor)
This work deals with designing a library of processor models used in embedded systems. Processor architectures are described using the ISAC language. The ISAC language is one of several outcomes of the Lissom project that is taking place at the Faculty of Information Technology, BUT, Brno. The beginning of this work is aimed to provide the introduction to processor architectures used in today's embedded systems. Remaining sections are devoted to presentations of exemplary processor architectures and the description of their implementation. This work is finalized by concluding the gathered experience with emphasis on the suitability of the ISAC language for architecture description and the efficiency of its simulation.
Fixed and Floating Point Arithmetic Elementar Processor
Čambor, Michal ; Kraus, Michal (referee) ; Kunovský, Jiří (advisor)
This thesis is about the concept of elementar processor. This processor solves of differential equations using Eulerian equation. The thesis consists of two major parts. In the first one the processor uses fixed point arithmetic. The second part tackles the problem of floating point arithmetic.
Membraneless speaker
Kovář, Josef ; Šteffan, Pavel (referee) ; Pavlík, Michal (advisor)
The bachelor thesis consists of theoretic basics and describes the design and construction of one-channel membraneless speaker. Absence of mechanical components gives the membraneless speaker no frequency limitation. The design consists of power source, control electronics, which modulates the signal, convertor and output transformer. The power source is realized by transformer, which lowers the voltage and stabilizators. Modulation is provided by integrated circuit TL 594, its duty is adjusted by potentiometer P1 and frequency by potentiometer P2. Power conversion provides dual forward converter. As a output transformer was used transformer from color television.
Modification of Vocal Tracks in SW Post-Production of Music
Trkal, Tomáš ; Beran, Vítězslav (referee) ; Černocký, Jan (advisor)
This thesis describes a design and an implementation of a vocal tracks processing application. The application consists of several sub-modules representing audio processors and effects. It is implemented as a plugin created with the VST technology. The plugin provides a simple control system and an integrated database of presets which help mainly less experienced users to significantly speed up the process of processing the vocal tracks. The user evaluation shows that application is successful both in creating demos and professional mixing of music tracks.
RISC-V Model Creation
Nosterský, Milan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description  CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.

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