|
|
Dynamic Approximation of Digital Circuits
Jásenský, Michal ; Hrbáček, Radek (referee) ; Sekanina, Lukáš (advisor)
This bachelor's thesis deals with design of a method based on cartesian genetic programming, which allows the evolutionary design of circuits capable of dynamic reconfiguration. The goal of reconfiguration is to dynamically change the number of used components and thereby to change the accuracy of calculation. In this thesis, implementation of the proposed method is described. The method is experimentally verified and demonstrated on several selected circuits.
|
|
|
Coevolution of Image Filters and Noise Detectors
Komjáthy, Gergely ; Zachariášová, Marcela (referee) ; Drahošová, Michaela (advisor)
This thesis deals with image filter design using coevolutionary algorithms. It contains a description of evolutionary algorithms, focusing on genetic programming, cartesian genetic programming and coevolution, the reader can learn about image filters too. The next chapters contain the design of image filters and noise detectors using cooperative coevolution, and the implementation and testing of the proposed filter. In the last chapter the proposed filter is compared to other filters created using evolutionary algorithms but without coevolution.
|
|
|
Geometric Semantic Genetic Programming
Končal, Ondřej ; Bidlo, Michal (referee) ; Sekanina, Lukáš (advisor)
This thesis examines a conversion of a solution produced by geometric semantic genetic programming (GSGP) to an instantion of cartesian genetic programming (CGP). GSGP has proven its quality to create complex mathematical models; however, the size of these models can get problematically large. CGP, on the other hand, is able to reduce the size of given models. This thesis combinated these methods to create a subtree CGP (SCGP). The SCGP uses an output of GSGP as an input and the evolution is performed using the CGP. Experiments performed on four pharmacokinetic tasks have shown that the SCGP is able to reduce the solution size in every case. Overfitting was detected in one out of four test problems.
|
|
|
Genetic Improvement of Cartesian Genetic Programming Software
Husa, Jakub ; Jaroš, Jiří (referee) ; Sekanina, Lukáš (advisor)
Genetic programming is a nature-inspired method of programming that allows an automated creation and adaptation of programs. For nearly two decades, this method has been able to provide human-comparable results across many fields. This work gives an introduction to the problems of evolutionary algorithms, genetic programming and the way they can be used to improve already existing software. This work then proposes a program able to use these methods to improve an implementation of cartesian genetic programming (CGP). This program is then tested on a CGP implementation created specifically for this project, and its functionality is then verified on other already existing implementations of CGP.
|
|
|
Movement Abnormalities Classification using Genetic Programming
Chudárek, Aleš ; Mrázek, Vojtěch (referee) ; Drahošová, Michaela (advisor)
When suppressing the symptoms of Parkinson's disease, the correct dosage of drugs is critical for the patient. Improper dosing can either cause insufficient suppression of symptoms or, conversely, side effects, such as dyskinesia, occur with high doses. Dyskinesia is manifested by involuntary muscle movement. This work deals with the automated classification of dyskinesia from motion data recorded using a triaxial accelerometer located on the patient's body. In this work, the classifier of dyskinesia is automatically designed using Cartesian genetic programming. The designed classifier achieves very good quality of classification of severe dyskinesia (AUC = 0,94), which is a comparable result to the techniques presented in scientific literature.
|
|
|
Acceleration of Symbolic Regression Using Cartesian Genetic Programming
Hodaň, David ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
This thesis is focused on finding procedures that would accelerate symbolic regressions in Cartesian Genetic Programming. It describes Cartesian Genetic Programming and its use in the task of symbolic regression. It deals with the SIMD architecture and the SSE and AVX instruction set. Several optimizations that lead to a significant acceleration of evolution in Cartesian Genetic Programming are presented. A method of a bit-level parallel simulation that uses AVX2 vectors allows to process 256 input combinations of a logic circuit in paralell. Similarly it is possible to use a byte-level parallel simulation and work with 32 bytes when evolving an image filter. A new method of batch mutation can accelerate the evolution of combinational logic circuits thousand times depending on the problem size. For example, using a combination of these and other methods the evolution of 5 x 5b multipliers took 5.8 seconds on average on an Intel Core i5-4590 processor.
|
|
|
Representation Techniques for Evolutionary Design of Cellular Automata
Kovács, Martin ; Drábek, Vladimír (referee) ; Bidlo, Michal (advisor)
The aim of this thesis is to experimentally evaluate the performance of several distinct representations of transition functions for cellular automata. Cellular automata have many potential applications for simulating various phenomena (e.g. natural processes, physical systems, etc.). Parallel computation of cellular automata is based on local cell interactions. Such computation, however, may prove difficult to program the CA, which is the reason for applying evolutionary techniques for the design of cellular automata in many cases. Evolutionary algorithms, based on Darwin's theory of evolution, have been used to find human-competitive solutions to many problems. In order to perform the evolutionary design of cellular automata, special encodings of the candidate solutions are often necessary. For this purpose the performance testing of various representations of the transition functions will be investigated. In particular, table representation, conditionally matching rules, and genetic programming will be treated. The problem of square calculations in cellular automata will be considered as a case study.
|
|
|
Employing Approximate Equivalence for Design of Approximate Circuits
Matyáš, Jiří ; Lengál, Ondřej (referee) ; Češka, Milan (advisor)
This thesis is concerned with the utilization of formal verification techniques in the design of the functional approximations of combinational circuits. We thoroughly study the existing formal approaches for the approximate equivalence checking and their utilization in the approximate circuit development. We present a new method that integrates the formal techniques into the Cartesian Genetic Programming. The key idea of our approach is to employ a new search strategy that drives the evolution towards promptly verifiable candidate solutions. The proposed method was implemented within ABC synthesis tool. Various parameters of the search strategy were examined and the algorithm's performance was evaluated on the functional approximations of multipliers and adders with operand widths up to 32 and 128 bits respectively. Achieved results show an unprecedented scalability of our approach.
|
|
|
Approximation of Digital Circuits in Yosys Tool
Plevač, Lukáš ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor)
The goal of this work is introduction of cgploss extension. This extension is extension for combinational logic circuits optimization in Yosys tool. Cartesian genetic programming is introduced in the first part of this work. Cartesian genetic programming is a design and optimization method that can be used for circuit optimization and approximation. This chapter introduces representation of combinational logic circuits for Cartesian genetic programming. The next chapter introduces Yosys tool and possibilities of the Yosys extending. The proposed 'cgploss' extension is introduced in the next chapter. The chapter also provides details about the implementation and the usage. The last chapter tests cgploss extension and compares representation of combinational logic circuits.
|
|
|
Acceleration of Transistor-Level Evolutionary Design of Digital Circuits Using Zynq
Mrázek, Vojtěch ; Sekanina, Lukáš (referee) ; Vašíček, Zdeněk (advisor)
The goal of this project is to design a hardware unit that is designed to accelerate evolutionary design of digital circuits on transistor level. The project is divided to two parts. The first one describes design methods of the MOSFET circuits and issues of evolutionary algorithms. It also analyses current results in this domain and provides a new method for the design and optimization. The second part describes proposed unit that accelerates the new method on the circuit Zynq which integrates ARM processor and programmable logic. The new method functionality has been empirically analysed in the task of optimization of few circuits with more inputs. The hardware unit has been tested for designing of gates on transistor level.
|
guest ::
