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Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator
Michl, Kamil ; Husár, Adam (referee) ; Zachariášová, Marcela (advisor)
This thesis is dealing with an option to connect the RTL simulation of a processor with a software debugger. Acording to my design, the communication between these components is handled using the JTAG and the Nexus interface. The simulation is controlled by a selected interface between hardware and software description languages. For the implementation, following components are used: JTAG adapter created by Codasip, RTL simulator Questa Advanced Simulator created by Mentor, a Siemens Business, and VPI interface for communication between Verilog and C++ languages. Concept presented in this thesis can be used on other implementations that depend on different programs and interfaces. The implementation contained in this thesis was tested and is fully functional. Nowadays, it is used by Codasip company and it will probably be updated and enhanced in the future.
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Generation of Object Files for RISC-V
Benna, Filip ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This master’s thesis deals with the topic of program source code compilation for RISC-V processor architecture. The generated object files need to be compatible with GNU binutils open source tools which are already available for the architecture. The focus is on relocations which must be correctly detected in Codasip Studio tools and transformed into RISC-V platform specific relocation types.
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Transformation of a Processor Description in CodAL to SystemC Structures
Ondruš, Tomáš ; Hynek, Jiří (referee) ; Přikryl, Zdeněk (advisor)
The goal of this thesis is to create a generator of simulators and hardware representation of application specific processors in a SystemC language. An aim of the first part is to create a wrapper layer compatible with SystemC TLM 2.0 that wraps an existing simulator to avail modeling of transaction oriented systems. The second part is a generator of a hardware representation for the processor that is suitable not only for logical synthesis, but also for the simulation on a cycle accurate level. A final result is a state of the art solution comparable to existing generators.
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RISC-V Model Creation
Nosterský, Milan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.
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NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
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Compilation of OpenCL Applications for Embedded Systems
Šnobl, Pavel ; Čekan, Ondřej (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for programming heterogeneous systems comprising processors, graphic accelerators and other computing devices. But it also finds usage on systems composed of just one computing unit, where it allows to write parallel programs (task and data parallelism) and work with hierarchical system of memories. In this thesis, various available open source OpenCL implementations are compared and one selected is then integrated into LLVM compiler infrastructure. This compiler is generated as a part of toolchain provided by application specific instruction set architecture processor developement environment called Codasip Studio. Designed and implemented are also optimizations for architectures with SIMD instructions and VLIW architectures. The result is tested and demonstrated on a set of testing applications.
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Modelling of 8051 Processor
Krůpa, Tomáš ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
Computer modeling is nowadays very important part of development of almost any new product. The objective of this bachelors thesis is to develop a model of 8051 microprocessor that should enlarge a portfolio of customizable processors available for Codasip platform. The complete model is described in two levels of abstraction the instruction accurate model and the cycle accurate model. For verification of the model, ANSI C programs translated by SDCC compiler were used.
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Functional Verification of Processor Execution Units
Valach, Lukáš ; Lengál, Ondřej (referee) ; Masařík, Karel (advisor)
The thesis deals with integration of functional verification into the design cycle of execution units in a hardware-software co-design environment of the Codasip system. The aim of the thesis is to design and implement a verification environment in SystemVerilog in order to verify automatically generated hardware representation of the execution units. In the introduction, advantages and basic methods of functional verification and principles of the Codasip system are discussed. Next chapters describe the process of design and implementation of the verification environment of arithmetic-logic unit as well as the analysis of the results of verification. In the end, a review of accomplished goals and the suggestions for future development of the verification environment are made.
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Information System for Software Licences
Nejedlý, Jakub ; Masařík, Karel (referee) ; Burget, Radek (advisor)
This work treats the creation of an information system for software license management. The ordering company is Codasip, which deals with processor manufacturing and creation of related software tools. This company has been using its web portal and licenses management system is its expanding module. That is why the source code of the project is written, as well as the original web interface, in PHP language, using the Nette Framework. Moreover there is the LM-X technology of software licensig described here and so the deployment in a rival solution. The specifications of the product by X-Formation and Codasip's requirements are setting the basics for license system design. The design itself and the description of the implementation according to MVP design pattern, are part of this work.
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Modelling of M68000 Model Processor
Adamec, Ondřej ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
The goal of this bachelor's thesis is to create a model of Motorola 68000 processor using architecture description language CodAL and Codasip development environment. Architecture of the processor is presented and model structure is described. The result is a working model that has been tested to ensure its correctness.
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