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Arithmetical completeness of the logic R
Holík, Lukáš ; Švejdar, Vítězslav (advisor) ; Bílková, Marta (referee)
The aim of this work is to use contemporary notation to build theory of Rosser logic, explain in detail its relation to Peano arithmetic, show its Kripke semantics and finally using plural self-reference show the proof of arithmetical completeness. In the last chapter we show some of the properties of Rosser sentences. Powered by TCPDF (www.tcpdf.org)
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Analysis of the CubeHash proposal
Stankovianska, Veronika ; Tůma, Jiří (advisor) ; Hojsík, Michal (referee)
The present thesis analyses the proposal of CubeHash with spe- cial emphasis on the following papers: "Inside the Hypercube" [1], "Sym- metric States and Their Improved Structure" [7] and "Linearisation Frame- work for Collision Attacks" [6]. The CubeHash algorithm is presented in a concise manner together with a proof that the CubeHash round function R : ({0, 1}32 )32 → ({0, 1}32 )32 is a permutation. The results of [1] and [7] con- cerning the CubeHash symmetric states are reviewed, corrected and substan- tiated by proofs. More precisely, working with a definition of D-symmetric state, based on [7], the thesis proves both that for V = Z4 2 and its linear subspace D, there are 22 |V | |D| D-symmetric states and an internal state x is D-symmetric if and only if the state R(x) is D-symmetric. In response to [1], the thesis presents a step-by-step computation of a lower bound for the num- ber of distinct symmetric states, explains why the improved preimage attack does not work as stated and gives a mathematical background for a search for fixed points in R. The thesis further points out that the linearisation method from [6] fails to consider the equation (A ⊕ α) + β = (A + β) ⊕ α (∗), present during the CubeHash iteration phase. Necessary and sufficient conditions for A being a solution to (∗) are...
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Algorithm for word morphisms fixed points
Matocha, Vojtěch ; Holub, Štěpán (advisor) ; Žemlička, Jan (referee)
In the present work we study the first polynomial algorithm, which tests if the given word is a fixed point of a nontrivial morphism. This work contains an improved worst-case complexity estimate O(m · n) where n denotes the word length and m denotes the size of the alphabet. In the second part of this work we study the union-find problem, which is the crucial part of the described algorithm, and the Ackermann function, which is closely linked to the union-find complexity. We summarize several common methods and their time complexity proofs. We also present a solution for a special case of the union-find problem which appears in the studied algorithm. The rest of the work focuses on a Java implementation, whose time tests correspond to improved upper bound, and a visualization useful for particular entries.
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Division Operation Simulation
Matečný, František ; Šátek, Václav (referee) ; Kunovský, Jiří (advisor)
This work deals with numerical integration and division operation. The reader is acquainted with the numerical solution of differential equations using division by the Taylor series. Next is explained the principle of SRT division in hardware and introduction of draft of design series-parallel and parallel division integrator in fixed point arithmetic. The practical aim of this work is implementation parallel division integrator and development of a software simulation of this integrator.
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Fractional-Octave Analysis of Acoustic Signals
Ryšavý, Marek ; Frenštátský, Petr (referee) ; Schimmel, Jiří (advisor)
The diploma thesis is focused on design and optimalization of digital octave and fraction-octave band filters. This thesis describe the behavior of filters in systems with fixed point arithmetics and investigate the impact of quantization coefficients for frequency response of filter. Filters, whitch has been designed, are implemented into simple software in C. Designed filters are in accordance with standard IEC 61260.
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Automatic Computation Control
Opálka, Jan ; Šátek, Václav (referee) ; Kunovský, Jiří (advisor)
This work deals with the automatic control of numerical calculations. The reader is acquainted with the numerical solution of differential equations and the parallel, serial, and series-parallel numerical integrator. The practical aim of this work is to design control circuits for the three mentioned variants of integrators. The design includes the development of a software simulator of the control circuit for the series-parallel integrator in a fixed point.
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Loading and Printing ASCII Numbers in FPGA
Závodník, Tomáš ; Zachariášová, Marcela (referee) ; Bartoš, Václav (advisor)
The topic of this work is the issue of processing decimal numbers using binary hardware units. Making use of specialized hardware for this purpose is problematic due to both number systems being incompatible. The thesis is focused specifically on fixed point decimal numbers passed in the form of ASCII character strings and on the FPGA technology. The proposed solution lies in creating hardware units that allow sequential loading and printing of decimal numbers in the mentioned form digit by digit. In terms of the content of this work, it introduces suitable algorithms and describes the realization of the proposed units. It results in their efficient, configurable, portable and reusable implementation.
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Audio equalizer implementation based on FPGA structure
Otisk, Libor ; Valach, Soběslav (referee) ; Kváš, Marek (advisor)
The bachelor thesis introduces the basic types of audio equalizers. It describes the design of digital filters for graphic equalizer, the correct choice of structure, placement and shape of digital filters. It also describes the implementation of graphic equalizer in the fixed-point arithmetic. It further describes an implementation of the algorithm graphic equalizer on PC and the implementation in gate array of FPGA.
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FPGA implementation of artificial neural network
Čermák, Justin ; Šteffan, Pavel (referee) ; Bohrn, Marek (advisor)
This master's thesis describes the design of effective working artificial neural network in FPGA Virtex-5 series with the maximum use of the possibility of parallelization. The theoretical part contains basic information on artificial neural networks, FPGA and VHDL. The practical part describes the used format of the variables, creating non-linear function, the principle of calculation the single layers, or the possibility of parameter settings generated artificial neural networks.
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